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Hi, I am currently trying to run simple RISC-V program with Sail emulator. I compiled it with cross compiler and trying to run it on an OCaml emulator. And I get the following error:
`CSR mstatus …
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in src/cpu.c ( lines 609-614 ) we have :
```
case ADDSUB:
switch (funct7) {
case ADD: exec_ADD(cpu, inst);
case SUB: exec_ADD(c…
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Hi,
I just ported your great little emu to a [very unlikely architecture](https://github.com/onnokort/semu-c64/) and whilst doing so, I had to tweak the MMU code to go through the RAM access method…
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When trying to follow the quickstart guide as in: https://riscof.readthedocs.io/en/stable/installation.html# the riscof run command at the very end fails.
I'm running on ubuntu a arm machine.
ri…
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When running a Rust code in VM , it becomes hard to trace back to Rust code from ELF. With debugging information it can be done. However we must enhance our runner to understand debugging information …
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I have tried to set PATH to `linux_for_riscv_em/output_mmu_rv32/buildroot/output/host/bin/`, I built the Linux kernel and it runs successfully in your emulator.
I think buildroot has built the tool…
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In this documentation page, https://riscof.readthedocs.io/en/latest/installation.html#install-plugin-models, there is an option to install the SAIL emulator as a docker image. After installing the doc…
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This project seeks a set of Ghidra import regression tests to validate sensible behavior after importing executable binaries into new versions of Ghidra. It's morphed somewhat into generating newer e…
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There is some relevant documentation included with the current RISC-V instructions decoding implementation. The maintenance and verification, however, are not straightforward. Instead, we may describe…
jserv updated
9 months ago
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Hi @AntonKozlov ,
Thanks for your effort on porting.
I am doning some work on porting OpenJDK for RISCV at the very begining but I have no idea how to start my work.
Could you share your roadmap or…