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test long branching
`./obj-rv32i_xcorevhwlp/bin/riscv32-unknown-elf-g++ -march=rv32i_xcorev1p0 -ftemplate-depth=1000 -c test2.cpp -o a.o`
`./obj-rv32i_xcorevhwlp/bin/riscv32-unknown-elf-objdump -d…
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I found that you are working on ztachip.I got issues with the micropython
I have done the ztachip build process , standalone image is working fine.
While going with micro-python ,I followed these st…
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Currently in the GCC compile we are running without any optimizations when we are compiling are test.
Will note that we are adding the optimization level -O3 only in the linker and the final compilat…
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Hi,
CHERIoT is spec'ed as being 16 GP registers only. However, in Sonata the RV32E is set to 0 which means that there are 32 GP registers. Shouldn't the RV32E parameter be set when the CHERIoTEn pa…
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> $ make BOARD=blackice-ii
> riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -Wall -Wextra -pedantic -DFREQ=48000000 -Os -ffreestanding -nostartfiles -g -Iprograms/hello -c -o programs/hello/main.…
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I build rv32im toolchain with the "build-rv32ima" script , changing the target compiler --with-arch=rv32im. Later I compile the program with "riscv32-unknown-elf-gcc -march=rv32i" and I measure the pr…
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The current VexRISCV configuration works well on big FPGAs like the Artix-7 and Spartan 6 but is too big for the tiny iCE40 based devices.
It would be good to add a variant which works well on the …
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RV32I does not require a PLIC, but Zephyr 1.13 does not run a riscv-privilege build without one, without modification to the Zephyr OS Core.
Can one build a non-riscv-privilege core (as far as Zeph…
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The GNU toolchain requires that the single letter extensions come first, followed by S*, H*, Z*, and X*. However, the table 27.1 lists 4 Z extensions as coming before the S* extensions. Since the GN…
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Here are a couple of examples of files sequences:
core1_freeze.txt:
```
W , 0x01C00150 , 0x0
W , 0x01C00154 , 0x0
W , 0x01C00158 , 0x0
W , 0x01C0015C , 0x0
```
core1_realease.t…