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VexRiscv-verilog
Using VexRiscv without installing Scala
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Fix VexRiscv_G Timing Take 2
#19
occheung
closed
2 years ago
1
Fix VexRiscv_G timing
#18
occheung
closed
2 years ago
2
Add VexRiscv_IMA_wide variant: 64-bits bus for RV32IMA
#17
occheung
closed
2 years ago
0
Patch PMP Plugin
#16
occheung
closed
3 years ago
0
Makefile: Generate fewer PMP regions
#15
occheung
closed
3 years ago
0
Add RV32G variant
#14
occheung
closed
3 years ago
0
VexRiscv_IMA: Enable Physical Memory Protection (PMP)
#13
occheung
closed
3 years ago
0
VexRiscv: Bump to 1.6.0 version of Spinal-HDL
#12
occheung
closed
3 years ago
8
VexRiscv_IMA: improve performance
#11
occheung
closed
3 years ago
0
Add RISC-V atomic options and RV32IMA variant
#10
occheung
closed
3 years ago
0
.gitmodules file contains local submodule value
#9
mithro
closed
4 years ago
2
Missing license information on generated files
#8
olofk
opened
5 years ago
0
VexRiscv-Min variant misbheaving
#7
smunaut
closed
5 years ago
14
VexRiscv 1.1 update
#6
Dolu1990
closed
5 years ago
0
Merging VexRiscv 1.1
#5
Dolu1990
closed
5 years ago
7
Add VexRiscv in full configuration
#4
mateusz-holenko
closed
5 years ago
4
Add Makefile and Various Configurations
#3
cr1901
closed
6 years ago
0
Add VexRISCV configuration suitable for iCE40 sized devices
#2
mithro
opened
6 years ago
19
Add debuggable version of the core
#1
xobs
closed
6 years ago
6