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Hi @dicecco1 ,
I want rebuild winograd_pe.xclbin, but I can't find winograd_pe.cl in src/caffe/ocl_caffe/convolution/winograd/, can you help update it?
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Hi, I am trying to build PipeCNN on Xilinx Device. However, the parameter POOL_LBUF_DEPTH required by conv_pipe_xilinx.cl has not defined in hw_param.cl. Any suggestion value for this parameter?
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I am currently facing some troubles while getting the SYCL compiler to run on a cluster equipped with Alveo U200 FPGAs. The cluster is running CentOS; unfortunately all default system tools are so anc…
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Hi,
I want to do some performance stuff on FPGA with Intel FPGA OpenCL SDK.
But have a question that does this support FPGA too? @gicmo @hughperkins @robertsdionne @sschaetz @glehmann
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Hello,
Today I was trying to connect to the AWS instance using remmina for which i followed the set-up guide. But once I hit connect I get error saying that its a error :VNC problem connecting, and…
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How much work is required to set up development on Xilinx FPGAs? What is the status of the project vis-a-vis Intel's Clang SYCL? Is there a chance of Intel's SYCL compiling to Xilinx FPGAs? What is th…
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Compiling for FPGA. This process may take a long time, please be patient.
Error (184036): Cannot place the following 204 DSP cells -- a legal placement which satisfies all the DSP requirements could …
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Making 'run_hw' seems work OK, but it reports ```/bin/bash: xclbin_get_freq.pl: command not found```, which can be found from the message below.
```
$ make run_hw SDA_FLOW=hw GEMX_ddrWidth=32 GEMX_…
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### Macros
In the current semantics of Fuse, there are no true "functions". All `def`s in the semantics should be thought of simple macros that just get expanded at call locations. This notion corres…