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Hi,
how can I replace all the occurrences of a specific verilog parameter with their value?
I mean, suppose I have "parameter [3:0] x = 4'b3;" and then a lot of usages of x, I'd need to effectively…
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hello, i am a new programmer. i want to write a tools then share it with others。
the python version is: Python 3.6.5 (v3.6.5:f59c0932b4, Mar 28 2018, 16:07:46) [MSC v.1900 32 bit (Intel)] on win32
p…
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I'm requesting to make it possible to treat Block RAM explicitly in veriloggen. I want to create line-buffer which is composed of register and BRAM.
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FPGA world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help everyone, so HDL implementations wi…
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Thanks for the great work on this module! I suggest adding support for the iverilog **-y** option (libdir, see http://iverilog.wikia.com/wiki/Iverilog_Flags). This makes it easy to run simulations w…
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Hi, I need to make a verilog module that calculates a boolean expression from an equation given as a string in python, Would you have an example of how to do this using veriloggen?
Ex:
python:
exp…
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