PyHDI veriloggen issues

PyHDI / veriloggen

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

Apache License 2.0

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issues

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License does not have year or author clause

#63 lemoncmd opened 1 month ago
0
Jupyter notebook 'hello_led.ipynb'

#62 zehonyi21 opened 2 months ago
1
Java runtime error

#61 VPIgnite99 opened 7 months ago
0
# The task call part in veriloggen library is not generated correctly

#60 Hikakkun opened 8 months ago
0
chore: update gitignore for python

#59 t-ngtn closed 11 months ago
0
read_verilog_module does not support instances with unconnected ports, will generate a TypeError.

#58 darcy-wu opened 1 year ago
0
Multi instance using the same module

#57 panwenzong closed 1 year ago
5
Add f-strings support in `print()` within threads

#56 estodi closed 1 year ago
0
fix and update thread_matmul_ext_onchip_ram

#55 estodi closed 1 year ago
0
add stypes.RandXorshift

#54 sh-mug closed 1 year ago
0
Add OpenLane Support

#53 mu2519 opened 1 year ago
0
typo in stream/stypes.py line 52

#52 mayagokhale closed 1 year ago
1
`types.AxiMaster` should be have a cap of number of outstanding readout transactions.

#51 RyusukeYamano closed 1 year ago
1
Convention violation of AXI Lite protocol on AxiLiteSlave

#50 RyusukeYamano closed 1 year ago
1
Imcompatibility of `Module.Wire` and `Module.TmpWire` regarding the keyword arguments.

#49 estodi closed 1 year ago
1
Support for binary operations with _Numeric class in the right term

#48 sh-mug closed 1 year ago
0
Slice in Wire with two dimension

#47 LucasBraganca opened 2 years ago
1
Creating a combinational sequence

#46 kiteloopdesign opened 3 years ago
0
Case statement within combinational block

#45 kiteloopdesign closed 3 years ago
2
to_verilog("file.v") creates two empty lines at beginning of file

#44 kiteloopdesign opened 3 years ago
0
Creating input with literal BW in the form of [n:0] instead of [n-1:0]

#43 kiteloopdesign opened 3 years ago
0
Support for SystemVerilog Interfaces

#42 kiteloopdesign closed 3 years ago
2
always @ ( * ) combinational block

#41 kiteloopdesign closed 3 years ago
2
deleted

#40 shtaxxx closed 3 years ago
0
stream.source with only size without data read

#39 shtaxxx opened 3 years ago
0
Bug of stream.ReduceDiv for signed values

#38 shtaxxx opened 3 years ago
0
Inserting user-defined simulation code for Verilator mode

#37 shtaxxx opened 3 years ago
0
Infinite read size for stream.source

#36 shtaxxx opened 3 years ago
0
modify linebuffer2d test as upsampling(4x4 -> 8x8)

#35 lp6m closed 3 years ago
0
Modify stream linebuffer2d_2

#34 lp6m closed 3 years ago
0
add stypes.LineBuffer

#33 lp6m closed 3 years ago
0
Explicit latency constraint between two stream objects which accesses to external resources outside of the stream.

#32 shtaxxx opened 4 years ago
1
modify bug in readRAM when latency = 2

#31 lp6m closed 4 years ago
1
Issues/54 add interval option to stypes.Counter

#30 lp6m closed 4 years ago
1
Supports IP-XACT format interrupt signals.

#29 smilengineer closed 4 years ago
0
fix Sra rounding

#28 RyusukeYamano closed 4 years ago
0
Supporting indirect addressing by sink RAM of Thread.Stream

#27 shtaxxx closed 3 years ago
1
Supporting multiple outstanding DMA requests

#26 shtaxxx opened 5 years ago
1
memcpy between on-chip RAMs

#25 shtaxxx closed 3 years ago
1
Online tutorial on binder/jupyter

#24 shtaxxx opened 5 years ago
0
Travis CI -> CircleCI?

#23 shtaxxx opened 5 years ago
4
Supporting explicit Block RAM generation

#22 iitaku closed 5 years ago
1
Supporting AXI Stream interface

#21 iitaku closed 3 years ago
3
How to use from_verilog function in veriloggen

#20 bhargav3333 opened 5 years ago
1
Better Documentation/Tutorials

#19 xd009642 opened 5 years ago
6
Help with design of low-level HDL language

#18 XVilka closed 5 years ago
1
Indirect access RAM in Veriloggen.Thread.Stream

#17 shtaxxx closed 3 years ago
1
realtime monitoring of simulation output

#16 sgherbst opened 6 years ago
1
iverilog libdir option

#15 sgherbst closed 6 years ago
1
Help, how to make a verilog module from a Boolean expression

#14 LucasBraganca closed 7 years ago
4