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There is a comment from @bader:
> @AlexeySachkov, I would prefer if we disable vectorizers only for SPIR target as I noted here. So if Xilinx FPGA uses different triple, it can still control the de…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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I got new TE0712 modules. On a working setup, I replaced an old programmed modules with the new module. I could load the bitfile to FPGA, and the board worked as expected until reboot/repower. Then …
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I'm having troubles while running a simulation of the JPEG Encoder (jpeg.encoder.hw.Encoder in the JPEG orc-apps repo). The behavioral simulation is correct, but, in the post-synthesis one, some token…
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```
ERROR: [CFGEN 83-2291] --sc tag applied with invalid slave kernel instance: batchNorm_1
ERROR: [CFGEN 83-2291] --sc tag applied with invalid master kernel instance: batchNorm_1
ERROR: [CFGEN 83…
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When I try to open the post place & route implementation in fpga_editor from the tools menu, I get this error:
`/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/_fpga_editor: error while loading shared librar…
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Hi
I am trying lowrisc-chip v0.7 by the command:
make nexys4_ddr_ariane
I do source the vivado path by
source /tools/Xilinx/Vivado/2018.3/*.sh
and
which vivado
do found the path of vivado.
…
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Could this project add Xilinx Virtual Cable Support? JTAG and programming are very solid in this project, found some other XVC project, like https://github.com/kholia/xvcpi and https://github.com/Berk…
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Hi, I'm working on the step 4: Compile the overlay project on Vivado 2022.2, ubuntu 20.04. And the kria-vitis-platforms branch is [xlnx_rel_v2022.1].
When it comes to the command `source -notrace .…
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`bootgen` has the option `--process_bitstream` which converts a `.bit`-format bitstream to the raw byte-swapped format that is also used in a normal boot image, but without all the headers of a normal…