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Hi
I am trying lowrisc-chip v0.7 by the command:
make nexys4_ddr_ariane
I do source the vivado path by
source /tools/Xilinx/Vivado/2018.3/*.sh
and
which vivado
do found the path of vivado.
…
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```
Launching Docker daemon and XQuartz...
Building Docker image
[+] Building 799.2s (15/15) FINISHED docker:desktop-linux
=> [internal] load build definition from Dockerfil…
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Ran make nexys4_ddr_rocket with Vivado 2018.3
and have ERRORs
any hint ?
WARNING: [filemgmt 56-315] Source scanning failed during design analysis. To get more details run synthesis or simulation …
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- [x] Triggering based on custom Verilog in FPGA
- [x] Xilinx interrupt controller configuration on C code side
- [ ] #349
- [ ] #350
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Hi
I use a JTAG HS2 probe on a JTAG chain with an artix7, I use the bsdl file provided by xilinx and I can not read ID, or scan an I/O.
Do you need to have a blank FPGA for this to work, the HS2 pro…
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@nandor and I have stumbled across the following interesting discrepancy between MFC and SFC when running the resulting Verilog through Vivado and comparing the number of DSP slices used (`PipelinedMu…
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Goals:
- [ ] Why ZCU is outputting 10 MHz instead of 400 MHz?
- [ ] Set up memory map and spacely to write and read from Cristian's firmware
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Hi,
I am one of the early purchasers for your Mercury 1 board and have contacted you a couple of years back regarding Linux support for Mercury board. I am glad that there is Linux support now for yo…
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Hi,
First of all thanks for the great project. I wanted to know the difference between nextpnr-fpga-interchange and nextpnr-xilinx and in which part of the project RapidWright is used. My guess is th…