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https://github.com/schoeberl/cae-examples provides a bare-metal test for riscv.
Running it with:
```
qemu-system-riscv64 -nographic -S -s -kernel test
```
And stepping it through gdb with:
`…
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I don't know if this is handled by Andy Ross' updates to the timer stuff, so rather than it getting dropped:
riscv_machine_timer_irq_handler in drivers/timer/riscv_machine_timer.c
is presumably the …
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I am planning to cleanup linux GPIO & PWM driver for Unleashed board.
Can I access the specs for these devices ?
@palmer-dabbelt @terpstra
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When I user command "spike bbl vmlinux" to boot linux,I encountered the error:"Cannot open root device "generic-blkdev" or unknown-block(0,0): error -6",and stuck at：“ret_from_syscall+0xc/0x10”. What'…
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Hello guys,
I’ve been implementing Xilinx Ultrascale VCU118 (Sifive core + NVDLA) these days. I cloned the master branch of freedom and compiled using `Makefile.vcu118-iofpga-nvdla`… the timing is …
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I've got a project based on the Freedom design. I've just rebased our stuff on top of the latest in rocket-chip's master branch and now see a bunch of issues with chiplink, it primarily seems to do wi…
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when excuted a sample test by using command spike pk test，but the error happened is as follows.
"
terminate called after throwing an instance of 'std::runtime_error'
what(): couldn't allocate 2…
awxhw updated
6 years ago
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I want to build a sifive port for supporting **ISA-rv64ima**.Here I am modifying makefile, instead of "ISA ?= rv64imafdc" i am planing to change "ISA ?= rv64ima" and here question is what to give inst…
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```
>>> libtirpc 1.0.1 Updating config.sub and config.guess
for file in config.guess config.sub; do for i in $(find /home/spaceboyross/TheBlueSystem/freedom-u-sdk/work/buildroot_initramfs/build/libt…
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Hi,
I am looking for UART driver address location and related information. I do find options to configure UART at different location for luminarymicro. Is there something similar there for RISCV po…
ghost updated
6 years ago