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Hello,
I have not been able to find any TRD for a U250 DPU based on DPUCADF8H. The u200 example for the waa resnet50 is a good baseline, but I need to deploy my app on the Azure cloud which uses a U2…
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i build and install xrt_2019.2 on ubuntu 18.04,
(1) lspci -vvv -d 10ee:
xclmgmt and xocl kernel driver can be recognized
(2) sudo /opt/xilinx/xrt/bin/xbmgmt flash --scan
Flashab…
crizy updated
2 years ago
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Hi,
I am trying to run Corundum using Alveo U250. It seems that I can see two interfaces in my host after installing mqnic kernel module. But I do not know whether the HW works correctly
Here is…
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This is a non-exhaustive list of some larger problems relating to XIlinx FPGA compilation and runtime execution (some with more information than others) that need some thought long term:
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Hello, World!
We are a group intending to accelerate some Pytorch operations on Xilinx UltraScale FPGAs. However, we are a little lost to where to begin to port the functions.
From what we could…
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The libreqos.io project is using XDP + EBPF + cake to schedule packets for 10s of thousands of customers. There appears to be a performance wall we are going to hit as we try to crack 40Gbit. In looki…
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I've just got this problem while building the driver. So I'm using an Alveo U200 100g version, I've installed the kernnel source code and its headers, I ran the synthesis and implementation and gener…
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I've been trying to generate the bitstream targeting VCU118 for benchmark purposes.
To generate the bitstream, [the wiki](https://github.com/fpgasystems/fpga-network-stack/wiki/Getting-Started-Guid…
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Hello.
I have a question about the usage of nanotube-generated HLS modules.
I'd like to know what I should connect to the input and output of the AXI-Stream chain.
### What you are trying to do.
…
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Thanks a lot for open-sourcing the verilog source code and corresponding bitstreams. I followed the instructions for the basys3 board trace collection and performed the CPA using the provided scripts.…