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**Issue by [whitequark](https://github.com/whitequark)**
_Thursday Aug 22, 2019 at 21:49 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/184_
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A number of people have express…
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Hi,
To my understanding, this repo is now currently only for FPGA implementation, so I wonder if your team plans to target any ASIC implementation in the near future? Or do you know of any finished…
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### Problem
Currently, we have no verification that the chips are receiving the data sent to them. We're sending the data blindly.
Create a script that captures the return data from the ASICs after …
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https://github.com/Nitheeshkumar521/asic-design-class/blob/main/asiclab1image.jpeg
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Antminer and baikal
When I point rig monitor to asic as sgminer there is problem to decode response and no data shown in rig monitor
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What is the estimated speedup of the design as an ASIC, given smaller feature sizes and hence higher clock speeds? Could this possibly be 10x?
Further, I notice that the number of clk/sq for pearso…
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Trigger FW update with chosen source
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With ASIC's coming out soon I wonder how difficult would it be to implement?
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Hi, I generated a verilog module for the litedram core and now I want to simulate it as as ASIC design, basically I am trying to dummy out those interfaces with FPGA.
Existed bench are all FPGA bas…
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![image](https://user-images.githubusercontent.com/634220/134489904-ad91caf9-d777-4aa2-9f79-59d5b893829e.png)