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Are there any proposals to integrate CHERI with the RISC-V debug and trigger extensions? At a minimum, there will be some debug and trigger CSRs that will need to be promoted to SCRs such as `dscratch…
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`SCBNDSI` has a 5-bit immediate, `uimm`, and a gated (by `s`) shift-by-4 operation, in
https://github.com/riscv/riscv-cheri/blob/1c43ce2fe5688057d6108a5f901574f2dac0acd0/src/insns/scbnds_32bit.adoc?p…
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Upstream RISC-V privileged specification as of 20211203 defines 3 additional PTE bits for the Svnapot and Svpbmt extensions that conflict with the existing CHERI PTE bits. The simplest workaround for…
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As per https://github.com/microsoft/cheriot-sail/issues/56 recent dev versions of Sail have started to give an odd type check failure compiling the CHERIoT sail model. It looks like this might be comm…
rmn30 updated
4 months ago
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For example, if I don't have `lem` cloned, I get...
```
$ ~/cheri/cheribuild/cheribuild.py lem
Will execute the following 1 targets:
lem
/usr/bin/opam --version
cd /home/nwf/cheri/lem && en…
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A naive question, I want to modify CHERI RISC-V ISA by adding an crypto instruction so compiler should also need to be modified to generate instruction. Is there any document of workflow that how many…
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I'm trying to build this using the current HEAD and it fails with this error:
Updating crates.io index
error: failed to select a version for `compiler_builtins`.
... required by package `…
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```
/home/ciyan/phd_proj/cheri-riscv/output/sdk/bin/clang -target riscv64-unknown-freebsd13 --sysroot=/home/ciyan/phd_proj/cheri-riscv/output/rootfs-riscv64-purecap -B/home/ciyan/phd_proj/cheri-riscv…
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CHERI adds some extra hardware functionality which software can take advantage of to do advanced memory protection and such.
https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/
https://www.cl.c…
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I propose merging CHERI exceptions and priorities with standard RISC-V exceptions.
I also propose adding a new CSR to hold additional additional informatin on a load/store exception so that `mtval/st…