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The following code
```python
class Foo(m.Circuit):
T = m.Array[8, m.Bits[6]]
S = m.Array[4, m.Bits[6]]
io = m.IO(
I=m.In(T),
O=m.Out(S),
)
io.O @= io.I…
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Dillon has helped us create a simulation plugin in the coreIR interpreter to simulate the unified buffer functional model with PE and other logic. Is that possible to have pycoreir supported these fun…
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Was having problems with trying to get the magma_tutorial working as it silently dies during compile and run. I made a smaller case: test.py
from magma_tutorial.adder import DefineAdd_
import faul…
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I remembered one idea on how to do this based on our meeting with priyanka
Supposed we had this circuit
```verilog
module coreir_add #(parameter width=1) (
input [width-1:0] in0,
input [wid…
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Tentative features for next major release of Magma
- [ ] New type system
- [x] bracket syntax Bits[n] instead of Bits(n)
- [x] product types
- [ ] sum types
- [x] Consistent with hw…
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https://github.com/David-Durst/aetherling/blob/sim_issues/tests/helper_test_readyvalid.py#L54
This causes CoreIR to segfault and the simulator to stop. This shouldn't be a segfault. Not sure if thi…
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We don't actually have 16-bit NOT in the current PE implementation, despite that it's somewhere in the hardware spec. Depends on what's implemented in CoreIR, we need to replace it with either a compa…
Kuree updated
6 years ago
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@jeffsetter now unsharp has an error in its compute units:
```bash
ERROR in compute unit: hcompute_ratio_stencil
in0_blur_unnormalized_stencil[0] -> 63743
in0_blur_unnormalized_stencil[0] -> 1…
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- [x] Cheat sheet/language spec (ala Chisel's cheat sheet https://inst.eecs.berkeley.edu/~cs250/sp17/handouts/chisel-cheatsheet3.pdf), Raj
* [magma cheat sheet](https://github.com/phanrahan/magma/b…
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Not sure why coreir and verilator examples are in this repo.