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This is a primitive Property operation, defined by FIRRTL spec section 25.1.1. General folds for signed arbitrary precision integer arithmetic can be applied, but none were defined in the initial PR. …
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Some big apps get random firrtl errors, so it seems the best way to bypass this is to use protobuf inbetween chisel and firrtl to avoid the firrtl parser. This should also speed up compile times.
…
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**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**Other information**
I want to generate mem tarce using the script `tracegen.py`. But I c…
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I executed `make emulator` on Centos7.9.
I hope it's linux-x86_64.
```txt
[info] Compiling 1 protobuf files to /trunk/branch/essent-rocket-demo/rocket-chip/firrtl/target/scala-2.12/src_managed/m…
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When Idea in debug mode it will StackOverflowError
There are recursive happend, how do i modify those code
///
Exception in thread "main" java.lang.StackOverflowError
at firrtl.transforms.Const…
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I have an internal signal:
`val state = Vec(Reg(init = Bool(true)) +: Seq.fill(p.numBits)(Reg(init = Bool(false))))`
In the PeekPokeTester, I try
`peek(c.state)`
and get
```
[info] - should gene…
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I'm attempting to use the command provided in the README (`sbt "runMain chiselucl.FirrtlToUclid $PATH_TO_FIRRTL_FILE"`) to convert a FIRRTL file to a uclid model, and encountering an error. The input …
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The code passes the test:
```
class RealGCDInput extends Bundle {
val a = UInt(16.W)
val b = UInt(16.W)
}
class RealGCD extends Module {
val io = IO(new Bundle {
val in = DeqIO…
sols1 updated
7 years ago
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In Chisel we are seeking for intrinsics for sampled value functions like `$rose` and `$stable` to use with LTL and I think it should be lowered to the `sv` dialect in CIRCT.
I noticed that there ar…
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I have started to work on a better version for my type-based waveform viewer for [Tydi](https://github.com/ccromjongh/Tydi-Chisel) and Chisel-related projects (Tywaves).
My chisel fork: https://git…