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### Before start
- [X] I have read the [RISC-V ISA Manual](https://github.com/riscv/riscv-isa-manual) and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册,这不是一个指令集相关的问题。
- [X] I have read the […
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The following is currently failing:
```
FIRRTL version 4.0.0
circuit Foo:
module Foo:
wire x: UInt
node y = {|some: UInt, None|}(Some, x)
```
~The problem is that this is parsing…
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I'm attempting to use the command provided in the README (`sbt "runMain chiselucl.FirrtlToUclid $PATH_TO_FIRRTL_FILE"`) to convert a FIRRTL file to a uclid model, and encountering an error. The input …
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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The code passes the test:
```
class RealGCDInput extends Bundle {
val a = UInt(16.W)
val b = UInt(16.W)
}
class RealGCD extends Module {
val io = IO(new Bundle {
val in = DeqIO…
sols1 updated
7 years ago
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The following fails verification after `circt-opt -lower-firrtl-to-hw`:
``` mlir
firrtl.circuit "Foo" {
firrtl.module private @Foo() {
%a = firrtl.wire : !firrtl.clock
%b = firrtl.inv…
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**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**Other information**
I want to generate mem tarce using the script `tracegen.py`. But I c…
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I executed `make emulator` on Centos7.9.
I hope it's linux-x86_64.
```txt
[info] Compiling 1 protobuf files to /trunk/branch/essent-rocket-demo/rocket-chip/firrtl/target/scala-2.12/src_managed/m…
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For any non-trivial design, the sizes of bundles can get very, very large. This is particularly apparent for modules which use libraries which auto-generate a ton of ports and put them all in the same…
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I'm trying to have FIRRTL automatically generate a scan chain when a "scan" bundle is included in my design.
Scan bundle = list of signals I want to have custom values for.
But since the added…