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Run command `make verify-la_test1-rtl` in _caravel_user_project_ fail with the current message:
`gf180mcuC/libs.ref/gf180mcu_fd_sc_mcu7t5v0/verilog/gf180mcu_fd_sc_mcu7t5v0_udp.v: No such file or dire…
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We're working on 3.3v and 1.8v cell libraries for GF180MCU. To allow designs with these with the current caravel, we would need an pin that could be assigned for the refernce VDD. We can then use leve…
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Looking at the current pcells, it seems that drawing the `LVPWELL` for nfet:
https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/blob/11770e5e5bae2a2072899e7ef282c080e6c5d762/cells/klay…
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## Expected Behavior
See https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/actions
```
[LVS | switch](https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pr/actions/r…
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If the intent was to follow the standard used by the sky130 PDK, then this is an epic fail. It needs correcting on multiple fronts.
For starters, the standard cell verilog modules make references …
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In order to enable https://github.com/efabless/caravel_user_project/issues/162 we need a version of the mgmt soc hardened with the current OpenLane gf180mcu-pdk support.
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## Expected Behavior
No Via resistance in tech lef
## Actual Behavior
Via resistance in tech lef
## Steps to Reproduce the Problem
1.
1.
1.
## Specifications
- Version:
- Platform:
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https://github.com/google/xls/issues/861 has made enough progress that we should start documenting the RAM support properly.
https://github.com/google/xls/blob/main/xls/examples/delay.x can be used…
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Just a possible improvement proposal and whenever I get a tiny bit of time would be most happy to help with it.
Since most existing open-source EDA tools generally are using ubuntu/debian distribut…