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### Background and motivation
This API proposal exposes methods to perform non-atomic volatile memory operations. Our volatile semantics are explained in our [memory model](https://github.com/dotne…
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Requested by Murray Kucherawy:
> The shepherd writeup says:
>
> "None of the IANA registries require Designated Expert Review."
>
> But this isn't quite correct, as [RFC 8126](https://datatrack…
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It's becoming a bit inconvenient to have all these folded instructions, aliases and syntactic sugars in the main semantics module, `wasm.md`. I suggest we move all rules that are just intermediate rew…
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this program in IR should exit with code 80
```llvm
define i64* @int_Index_int_int(i64* %_self,i64 %_idx) {
entry:
%_idx_0 = alloca i64
store i64 %_idx, i64* %_idx_0
%_4 = load i64, i64* %_self…
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This is a tracking issue for the RFC "Unsized Rvalues " (rust-lang/rfcs#1909).
**Steps:**
- [ ] Implement the RFC (cc @rust-lang/compiler -- can anyone write up mentoring instructions?)
- [ ] A…
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I'm aware that this is very much of a stretch-goal that I don't actually expect this to be fully done (and some are SVE ones so we don't have a good way to lift this), but I'm gonna post my list, so p…
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A C compiler can and will reorder non-volatile operations (even across sequence points). So I'm wondering if the enqueue/dequeue functions (e.g., in sddf/include/sddf/network/queue.h) need annotations…
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One aspect of the spec that makes it quite hard to read is the prose-based style. A good (bad) example of this is CSR fields, e.g. `mstatus`. It's easy enough to find the field diagram:
![image](ht…
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Hello all,
I'am studying how remill [lifts](https://github.com/trailofbits/remill/blob/master/remill/Arch/X86/Semantics/SSE.cpp#L1928) the `stmxcsr` instruction, but there are some details that I s…
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Seems Vexriscv by default has a 'simple' Ibus/Dbus implementation to fetch instructions and read/write data. What are the semantics of this bus? It seems AXI-like, but I cannot really find any details…