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## Description
Required wires in bus definitions are displayed as optional in bus interface port editor. Additionally, option to add only ports for either optional or required ports does not add an…
Kyrhe updated
5 months ago
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## Description
When writing verilog with generator from files, either diagrams or components, adding files to fileset causes the tool to crash. Writing verilog without fileset works correctly, for …
Kyrhe updated
5 months ago
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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The specs say that:
_dim (optional; type: unsignedLongintExpression (see C.3.8)) assigns an unbounded dimension to the register, so it is repeated as many times as the value of the dim elements_
S…
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This is a completely arbitrary example, but take the following:
```
0
```
There's no way to get both the name attribute and the 0, as tags designated as CHILD or CHILDREN in the ya…
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Hi everyone, can you please help me about this problem below:
1. When I use *RegblockExporter.export()* function to generate rtl code, I got an error like this:
```log
Traceback (most recent call …
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We started to work on resource handling. A very first idea is here: https://github.com/Open-CMSIS-Pack/devtools/blob/main/tools/projmgr/docs/Manual/Overview.md#cmsis-zone-integration
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As title,
I'd really like to know how did the value and parameterId come from? Is there any meaning for it?
Thanks in advance
BRs
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I spent 2h now figuring out why a generator was not working.
I figured out the installation of PeakRDL-python is pulling in peakrdl version 0.9.0, thus breaking other targets supported by version 1.1…
jeras updated
8 months ago
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## Problem
When running `peakrdl_cheader ./docs/rdl/ip_core.rdl --outdir export/c`, Peakrdl IPXACT plugin 'Peakrdl-ipxact' cannot be found under peakrdl.ipxact, but can be found under `peakrdl_ipxa…