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kactus2
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kactus2dev
Kactus2 is a graphical EDA tool based on the IP-XACT standard.
https://research.tuni.fi/system-on-chip/tools/
GNU General Public License v2.0
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ipxactexamplelib Validation failing with git main build
#115
AmeyaVS
opened
2 hours ago
0
HW designer instance parameter reverting
#114
Kyrhe
opened
3 weeks ago
0
HW designer design parameter menu does not appear
#113
Kyrhe
closed
3 weeks ago
1
HW designer crash occurance on dragging component
#112
Kyrhe
opened
1 month ago
1
SVD generator: redundant cluster layer
#111
hegza
opened
1 month ago
0
Bug: false errors on duplicate on component instantiation parameter
#110
Kyrhe
opened
2 months ago
0
About the memory design supports UVM RAL
#109
YuTienL
opened
3 months ago
0
Issue with port width evaluation formula with parenthesis
#108
Kyrhe
closed
3 weeks ago
1
Potential validator false error
#107
Kyrhe
opened
5 months ago
0
Bug: bus definition wire presence displays wrong value in bus interface port map editor
#106
Kyrhe
closed
5 months ago
1
Bug: Adding generated files to fileset crashes upon trying to write verilog
#105
Kyrhe
closed
5 months ago
1
Bug: Mirrored interface of 22 standard in HW diagram editor shows wrong colour
#104
Kyrhe
closed
5 months ago
1
Bug: copy of port type creates empty field
#103
Kyrhe
closed
4 months ago
1
Bug: Crash on manual port editor cancellation
#102
Kyrhe
closed
2 months ago
1
BUG: Draft component bus type mirrors assigned incorrectly
#101
Kyrhe
closed
4 weeks ago
1
BUG: Wiring from/to off-page wiring causes crash
#100
Kyrhe
opened
5 months ago
0
Missing feature: Port wire editor / create ports from interface
#99
Kyrhe
closed
5 months ago
1
BUG: Context menus open on different monitor
#98
Kyrhe
opened
5 months ago
0
make first execution Error
#97
Ryuji-Yatahagane
closed
6 months ago
2
Running Kactus2 on CentOS 7
#96
abdullahyildiz
closed
4 months ago
1
Qt6 requires purchase by commercial users
#95
lmg260a
closed
6 months ago
2
[CORRECTIVE] Fix incomplete QObject type and resolves errors
#94
vowstar
closed
7 months ago
0
Supporting alternate register
#93
DenizzzGuzell
closed
6 months ago
4
SVD generator guidelines.
#92
CalamaroS
opened
7 months ago
1
Qhelgenerator and Qmake not found
#91
Ryuji-Yatahagane
closed
8 months ago
2
Plugins are not available when using PythonAPI
#90
epekkar
opened
8 months ago
0
After generating VHDL lib. collapses
#89
DenizzzGuzell
closed
6 months ago
2
VHDL generation problems
#88
DenizzzGuzell
closed
8 months ago
2
Shutting down unexpectedly
#87
DenizzzGuzell
closed
6 months ago
4
[CORRECTIVE] add missing <QSharedPointer> include to fix QT6.6.0 build
#86
vowstar
closed
9 months ago
0
Build failed with QT 6.6.0 with incomplete type ‘QSharedPointer<Design>
#85
vowstar
closed
9 months ago
1
[CORRECTIVE] fix build PATH bugs about QT
#84
vowstar
closed
8 months ago
0
Missing Fields in Memory Maps Visualization
#83
pascal-creonic
closed
6 months ago
2
How do I generate svd files
#82
Yaozzheng
closed
8 months ago
4
Overriding component instance parameter from design is broken
#81
eyalherz
closed
8 months ago
1
Context Menu Options: "Open Containing Folder" and "Open XML File" Does not work on Linux
#80
AmeyaVS
closed
4 months ago
3
Fix Verilog Skeleton Generation
#79
AmeyaVS
closed
1 year ago
1
Remove Redundant Files Packaged on Windows Platform
#78
AmeyaVS
opened
1 year ago
0
Unable to run the latest commit on the master branch
#77
AmeyaVS
closed
1 year ago
3
Support for 1685-2022
#76
scottven
opened
1 year ago
2
Verilog Source Skeleton Code Generation Segmentation Fault.
#75
AmeyaVS
closed
1 year ago
3
Fix Compilation Error, Packaging for SWIG PythonAPI Generated file
#74
AmeyaVS
closed
1 year ago
4
Kactus2 for Win64 3.11.1: Bundled Python should be 3.8 instead of 3.10
#73
gaudat
closed
1 year ago
1
Build & Install on MACOS
#72
abrahamktm
opened
1 year ago
1
libIPXACTmodels.so.1
#71
Paul-Chaffey
closed
1 year ago
1
Configuring VHDL Generator to use entity instantiation.
#70
andrewandrepowell
opened
1 year ago
1
[CORRECTIVE] Fix VerilogPortParser find colon problem and ternary operators support
#69
vowstar
closed
1 year ago
1
[CORRECTIVE] Fix 1 bit port default value of verilog writer
#68
vowstar
closed
1 year ago
1
[PERFECTIVE] Optimize the default value of the verilog input port
#67
vowstar
closed
1 year ago
2
Unreasonable Python version dependency
#66
ktbarrett
opened
1 year ago
3
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