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Hi,
I just bought a digilent nexsys video FPGA card and run step -by step to boot Linux according which NaxRiscv document desicribed.
I can boot !!! and login from uart terminal.
But for HDMI o…
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Hello,
I'm playing with colorlight 5A75B board, with a etherbone client on it.
Now it's connected directly to pc ethernet port trough phy1 connector.
Would it be possible to daisy chain another sim…
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Hey, i used the following command `python3 -m litex_boards.targets.sipeed_tang_primer_20k --build --dock lite` to build a litex soc and after running it the memory init failed.
the following logs w…
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I have been testing Litex on the [Colorlight 5A-75B](https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/colorlight_5a_75b.py) board and I have connected to it with wishbone-too…
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# Introduction
In complex control systems, aspect of firmware updates distribution is critical for system development and maintenance. Due to the limited accessibility of some installations or thei…
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Hi everyone.
This issue is aimed to track the process of developing EasyNIC project.
The initial idea was introduced by @lukego . He also makes the spec https://github.com/lukego/easynic
Curren…
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Creating this item as work to discuss how to setup the FPU test environment for the marocchino FPU.
- *Main* Linux + GLIBC Math tests
- Bare metal - TestFloat
Other questions:
By the way. A…
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I was using the EtherBone host bridge to transfer large amount of data between PC and Arty A7 with 100Mbit Ethernet and experienced some performance issues. While write performance is sensible, read p…
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I am trying to get etherbone working with my butterstick, but it seems that litex_term and wishbone-tool are both failing to read the uart correctly when using --uart-name=crossover. All that is read…
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I am trying to reproduce the NaxRiscv/Debian setup as described [here](https://spinalhdl.github.io/NaxRiscv-Rtd/main/NaxRiscv/hardware/index.html) and am running into some issues.
Steps I have unte…