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Hi,
I recently developped a RISC-V OoO core and used Spike as a reference model in the verilator simulation of the hardware core. Got the simulation to keep spike and the core in exact sync while r…
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Generated Verilog file (https://github.com/tcal-x/pythondata-cpu-vexriscv/commit/5bb91146a62643cf606443d5366c69720906549c#diff-63516b47d7d1d76ef7a8d9ef1694bad1cec7d11cbfa4f872527bc3b4329dad12R3) point…
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Hi,
I've been working with SpinalHDL for a few months and am inspired by the design of NaxRiscv. I aim to deepen my understanding by building a toy CPU from scratch. While I appreciate the complexi…
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Hello,
I'm looking to generate the Verilog/Vhdl of a VexRISCV multicore SMP processor but rework its IO buto AXI. I see it has been done for a single VexRISCV core:
https://github.com/SpinalHDL…
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@Dolu1990 convinced me that even if SpinalHDL enables the user to abstract the wires, sometimes the user wants to manipulate wire-by-wire so aligning stuff would be great.
In https://github.com/num…
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Hi,
After running a program generated by riscv-dv for rv64imafdc, accessing address 0x7fffff20 generates an exception (trap_store_access_fault) in spike, but the DUT does the commit and RVLS detect…
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Hello,
The company I am currently working in finds SpinalHDL interesting for their top-level, to assemble all the components, because of the bus abstraction which generates normal wires in RTL. (If…
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Hi,
I found inconsistent results when using the shift instructions sraw and sraiw. These 64-bit-specific instructions perform the shift on the right-hand 32-bit part of the word and propagate the sig…
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AMBA5 CHI could be a good choice for high performance cache-coherent NOC design. However, it is kind of complex. How about building a NOC library with AMBA5 CHI? We can find its' specification book an…
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