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where can I find the verilog versions of the ztachip as Iam not familiar with the VHDL
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Hello,
I'm looking to generate the Verilog/Vhdl of a VexRISCV multicore SMP processor but rework its IO buto AXI. I see it has been done for a single VexRISCV core:
https://github.com/SpinalHDL…
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Hi,
I want to generate VexRiscv and Briey with Double FPU plugin. I'm a newby in SpinalHDL system. How can I do this? Thanks.
ghost updated
8 months ago
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Hi!
Feature suggestion: easily deriving one `.gtkw` file to have several ones, to show the same waves for different tests. For now I have an `sh` script, but maybe similar feature could be integrat…
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When bumping VexRiscv and pre-generated verilog to recent master, we saw hangs using the CFU using either locally generated verilog files, or those generated upstream. Original discussion here: htt…
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Hello,
The company I am currently working in finds SpinalHDL interesting for their top-level, to assemble all the components, because of the bus abstraction which generates normal wires in RTL. (If…
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With #8, I think the library will become interesting for a wider audience, now also including VHDL and Verilog users. However, at the moment the name of the library is rather generic. I think it would…
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Hi,
I was looking at some Coremark performance number to compare against https://github.com/SpinalHDL/NaxRiscv, but got multiple issues :
- Can't find any documentation about coremark performanc…
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outlog:
> "E:\Program\IntelliJ IDEA 2023.2\java_jb\bin\java.exe" "-javaagent:E:\Program\IntelliJ IDEA 2023.2\lib\idea_rt.jar=8529:E:\Program\IntelliJ IDEA 2023.2\bin" -Dfile.encoding=UTF-8 -classp…
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This is the first RISCV core I've been able to get up and running without breaking my head. Much appreciation for the SpinalHDL team for the making this work with Qsys and Avalon. :) (Although SpinalH…