-
I have used benchmark_sweep/counter8 task with k6_frac_N10_tileable_40nm architecture. Full testbench successfully runs and give expected results. However, within same task I also generate preconfigur…
-
HI,
I might got it wrong.
it seems to me that the hash value it got doesn't match the one shown online:
in particular, on the first vector, the input is 128 Byte: AED66CE184BE232900000010F149905…
-
I have installed cocotb on MacOS Catalina with a homebrew Python installation. I also have icarus verilog and verilator installed by homebrew.
OS: Catalina 10.15.5
Python 3.7.7
icarus-verilog 10.…
-
Thank you for the details on the previous issue I opened.
I have pulled the [latest commit](https://github.com/alchitry/Alchitry-Labs-V2/commit/08d1d6b340a8cf31a9976443dcfad2130582d600) you have a…
-
Hello,
I am using the most current version of CIRCT and I am having issues getting even some "basic" RTL to work properly. The behavioral simulation in Vivado 2021.2 is working correctly, but the p…
-
Hi all,
@SamuelDeleglise and I are currently trying to deal with the problem raised earlier in issue #415 : trying to phase-lock a two-laser beatnote with a reference signal at 40 MHz, we are limit…
-
Are ZB* bitmanip extensions supported? If yes, how do I specify supported ZB* extensions in isa.yaml
-
The irresistable draw of the MeCrisp family is the large installed base, and the promise that many of those implemented peripherals will also work on Mecrisp-Ice. The problem is that I do not know wh…
-
I successfully booted Linux with FPU disabled. When I enable FPU, I get the following errors:
```
[ 0.156632] smp: Bringing up secondary CPUs ... …
-
### Version
Yosys 0.39+165
### On which OS did this happen?
Linux
### Reproduction Steps
My Verilog original design is as follows:
```
module top (y, clk, wire3, wire2, wire1, wire…