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Tried to execute code (the one in the Xilinx repository) with newest version of RFNOC after having applied your patch to uhd-fpga. However the design does not synthesize.
I believe that the changes…
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The installation layout under `$PREFIX/lib` is a bit crowded and strange:
```
$ ls result/lib
Bluesim exec Libraries SAT tcllib Verilog Verilog.Quartus Verilog.Vivado VPI
```
This doe…
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I have a vunit fork [here](https://github.com/nfrancque/vunit) with some changes for our company's infrastructure that I'd like to get merged in where possible, this is the first one.
Would like he…
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We have started to do some work but we didn't have an issue for it so I'm creating one.
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I have Created a simulation project in vivado and then exporting that simulation for Questa. To run this simulation using Vunit environment I have created python script. Exported Simulation is creatin…
dsp20 updated
5 years ago
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Hi， are there the mentioned energy measurements available? Thanks!
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I wrote a [RISC-V processor](https://github.com/jeras/rp32) in heavy SystemVerilog with a lot of:
* arrays, `struct`ures, `union`s, `typedef`s, `enumeration`s, custom type `parameter`s, ...
* assign…
jeras updated
2 years ago
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Система тестирования должна поддерживать запуск нескольких разных элементарных тестов через скрипт.
Результатом тестирования каждого элементарного теста должна быть строка
* TEST PASSED - в случае п…
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Hi,
I am having problems with the paths in svunit.f file(s).
Consider the following directory structure.
```
/src/hdl
/src/hdl/svunit.f
/src/hdl/core/lib_01/*.sv
/src/hdl/core/lib_02/*.s…
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The current Calyx compilation flow involves running the native compiler to lower control operations into pure structure which can be exported back to the MLIR flow. @mikeurbach suggested that one way …