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It seems to be more consistent with most other commonly-known languages to have the syntax for a default case look like this:
```
with m.Switch(thing):
with m.Case(1):
...
with m.Case(2):…
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The reason `Value.part` exists in Migen (I think; @sbourdeauducq could confirm) is that it lowers directly to Verilog's indexed part-select construct: `x.part(s, N)` → `x[s+:N]`. Or at least was suppo…
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# [LiteX] Improve support for project IceStorm (Lattice ICE40 + OpenFPGA toolchain)
# Brief explanation
The first fully FOSS toolchain for FPGA development targets the Lattice ICE40 FPGA. LiteX …
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**Issue by [whitequark](https://github.com/whitequark)**
_Sunday Dec 16, 2018 at 10:21 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/7_
----
Migen left this undefined so we hav…
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If I define some signals in a module:
```
self.p1 = Signal()
self.p1.s = Signal()
```
and then assign it to a platform pad with subsignals, it works:
```
m.comb += plat.r…
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**Issue by [cr1901](https://github.com/cr1901)**
_Saturday Jul 06, 2019 at 23:07 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/130_
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## Actual Behavior
Example:
```
…
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**Issue by [whitequark](https://github.com/whitequark)**
_Sunday Jul 14, 2019 at 03:04 GMT_
_Originally opened as https://github.com/m-labs/nmigen/issues/148_
----
The reason `Value.part` exists in…
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17:26 < sb0> whitequark: https://github.com/m-labs/nmigen/blob/master/examples/alu_hier.py#L41-L42
17:26 < sb0> a typical bug is forgetting to add this in migen. would there be a way of addre…
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I am not sure if I am using `DomainRenamer` or `ClockSignal` wrong but I can't get them to work together.
```python3 from nmigen.hdl.xfrm import DomainRenamer
from nmigen import *
from nmigen.cli…
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I just discovered this bug in some oMigen code:
```diff
--- bad/software/glasgow/gateware/i2c.py
+++ good/software/glasgow/gateware/i2c.py
@@ -142,7 +142,7 @@ class I2CMaster(Module):
…