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I think it might make sense to group the generators into some categories;
* Analog generators (BAG / OpenFASoC)
* FPGA/CRGA generators (OpenFPGA / Fabulous)
* CPU generators (rocket, vexriscv,…
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If I do a quick reload of a snes rom through the "Load SMC" menu the save file will not be written properly. To get the save to stick I have to shutdown the pocket entirely.
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I saw that we can create synthesizable netlist via Fpga-Verilog that can be run into DC or some other synthesis tools in a webinar. Is it a different netlist type than generate_fabric task generate? I…
ghost updated
2 years ago
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I'm getting this error on my centos 7 machine when "make all" command was running.
My gcc version output is:
@localhost OpenFPGA]$ gcc --version
gcc (GCC) 8.3.1 20190311 (Red Hat 8.3.1-3)
Copy…
ghost updated
2 years ago
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The new CompilerOpenFPGA::Synthesize method runs yosys as a separate process.
Need to kill the process or close the pipe (Which should kill the process) when the stop command is pressed.
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I am able to execute the basic and, or gates using the default architectures, and default settings of the task configuration file. But, when I try to declare a 2-bit output/wire (output [1:0] and_out;…
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I want to run generate_fabric task on QLSOFA_HD to be able to reproduce exactly same Verilog netlists with the one in repo. So I configured **task.conf** file same with **task_generation.conf** in QLS…
ghost updated
2 years ago
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When I run compilation_verification using the blinking.v file i=given in the benchmark, the **00_blinking_MIN_ROUTE_CHAN_WIDTH_out.log** file is as given below:
RunDirectory : /home/user/OpenFPGA/…
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No error stack is showing currently, again some masking issue.
Users have to type puts $errorInfo to see the errors...
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If users already have open source `yosys` installed under path `/usr/local/bin` If user set PATH like PATH=$PATH: then as the `/usr/local/bin` comes first then system installed yosys is used. See the…