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**Is your feature request related to a problem? Please describe.**
OpenFPGA already has a complex CI/CD logic deployed on the Github Actions.
The CI consists of the following steps
- Detect any sou…
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Refs: #466, #829, #1152 and #1285.
Although there are multiple docker images available (https://hub.docker.com/search?q=yosys&type=image), AFAIK there is no 'official' one which is built in some CI…
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You might want to consider adopting the usage of the SymbiFlow Yosys Plugins @ https://github.com/SymbiFlow/yosys-symbiflow-plugins to improve your SDC support (and future timing driven synthesis). Th…
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[00_adder_4_MIN_ROUTE_CHAN_WIDTH_out.log](https://github.com/lnis-uofu/OpenFPGA/files/7357275/00_adder_4_MIN_ROUTE_CHAN_WIDTH_out.log)
Sorry to bother you again. As the log said, iverilog verificati…
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-Executables?
-TCL script into executable?
-Floorplanning python code
-Permutation python code
-Others?
Best to lock down the flow complete?
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Hello! I encountered several problems in the process of using openfpga,
1. When using script 1 for synthesis, the result is as shown in Figure 1, that is, _DFF_NP0_ and _DFF_NP1_ appear, but in k6_fr…
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Hi
We found a possibile bug when extracting the data.
The reproducing steps are shown as in the following.
1) Add the EPFL benchmark suits under dir **OpenFPGA/openfpga_flow/benchmarks**
2…
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Failed build with rustc 1.56.1 with issue:
```
🍺 /opt/homebrew/Cellar/rust/1.56.1: 30,858 files, 743.1MB
==> Installing twam/openfpga/nextpnr dependency: prjoxide
==> cargo install
Last 15 lines…
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I just noticed that the daily CI tests have been broken since we added them: https://github.com/siliconcompiler/siliconcompiler/actions/workflows/daily_tests.yml. Turns out they don't actually mark th…
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> **Describe the bug**
VPR Bug
When implementing the ISCAS '85 benchmark (specifically on the c2670, c5315, and c7552) Verilog circuits, VPR fails to translate the Verilog over to a fabric when usi…