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gatecat
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prjoxide
Documenting Lattice's 28nm FPGA parts
ISC License
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#46
mmicko
closed
8 months ago
0
ERROR: Cell type 'PCLKDIV' instantiated as 'U$$0' is not supported by this device.
#45
slagernate
opened
9 months ago
0
`prjoxide pack` fails for PLL on LIFCL-17
#44
siliconwitch
closed
8 months ago
1
libprjoxide: run `cargo fix`. NFCI
#43
whitequark
closed
1 year ago
0
Possible mistake in D-PHY routing
#42
robertszczepanski
closed
1 year ago
0
Add BRAM (PDPSC16K) memory inference example for lifcl-40-evn[g] board.
#41
slagernate
opened
1 year ago
0
Interface Not Read Correctly
#40
slagernate
closed
1 year ago
1
main router loop running indefinitely
#39
slagernate
opened
1 year ago
2
Unclear Error Message - High Performance Banks
#38
slagernate
closed
9 months ago
3
add lram example (for evn board)
#37
slagernate
closed
1 year ago
1
add lram example (for evn board)
#36
slagernate
closed
1 year ago
0
Could NOT find Boost (missing: iostreams) (f ound version "1.71.0")
#35
slagernate
closed
1 year ago
0
How to use Nexus memory modules?
#34
slagernate
closed
1 year ago
4
Feat/vvml example
#33
jmrobles
closed
1 year ago
2
prjoxide: update clap
#32
gburgessiv
closed
1 year ago
1
incorrect IDCode with LIFCL-40-8BG400CES device
#31
slagernate
closed
1 year ago
4
make: nextpnr-nexus: No such file or directory
#30
slagernate
closed
1 year ago
1
[WIP] Group LRAM timings by cell configuration
#29
mkurc-ant
opened
1 year ago
2
Update timing data and add LRAM timing
#28
gatecat
closed
2 years ago
0
Fix DCCs tilegrouping
#27
mtdudek
closed
2 years ago
4
Fix DCCs bel placement for top and bottom mux
#26
mtdudek
closed
2 years ago
4
devices.json: added LIFCL-40-ES2 IDCODE
#25
zavorka
closed
2 years ago
2
SEDC support?
#24
femtostar
opened
2 years ago
4
Fix 05-clock timing fuzzer
#23
mtdudek
closed
2 years ago
3
Timing fuzzer hotfix
#22
mkurc-ant
closed
2 years ago
0
Add PLL fuzzer for LIFCL-17
#21
mtdudek
closed
2 years ago
13
DCS support for LIFCL
#20
mkurc-ant
closed
2 years ago
2
build prjoxide with new rustc from homebrew package
#19
no111u3
closed
2 years ago
3
Crosslink VIP example - Incorrect device ID
#18
siliconwitch
closed
2 years ago
2
Question: can I get the git hash that a prjoxide executable was built at?
#17
tcal-x
opened
2 years ago
1
libprjoxide: Add LUT permutation pseudo-pips
#16
gatecat
closed
2 years ago
0
libprjoxide: Split VCC net for easier routing
#15
gatecat
closed
2 years ago
0
Are you looking for help with PCIe fuzzing?
#14
teknoman117
opened
2 years ago
2
Add LIFCL-17 SYSIO tiles to the 070 fuzzer
#13
mkurc-ant
closed
2 years ago
2
Fix issue compiling when clap 3.0.0-beta.4 came out
#12
mmicko
closed
2 years ago
0
Use num-bigint instead of rug and its GMP dependency
#11
whitequark
closed
3 years ago
2
Litex SoC does not boot on CrossLink-NX-17 with certain clock divisors (works in Radiant)
#10
danc86
opened
3 years ago
12
error with LRAM initial values on LIFCL-17: no IP named LRAM_CORE_R11C0
#9
danc86
closed
3 years ago
8
interchange: Hardcode LUT4 pin defaults
#8
gatecat
closed
3 years ago
0
interchange: Add pseudo-cell data for GND pseudo-pips
#7
gatecat
closed
3 years ago
0
interchange: Add LUT definitions
#6
gatecat
closed
3 years ago
0
interchange: Add IO and FFs
#5
gatecat
closed
3 years ago
0
Make cross compile possible
#4
mmicko
closed
3 years ago
1
Initial SymbiFlow arch interchange export
#3
gatecat
closed
3 years ago
1
bba: Switch from RelPtr to RelSlice
#2
daveshah1
closed
3 years ago
0
Building nextpnr looking for database files?
#1
davidcorrigan714
closed
3 years ago
3