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Hi, I compiled FSF GDB (v. 8.1.1) and also top-of-tree from the
`riscv-binutils-gdb` repository directly on the QEMU RISCV64 emulator, with
Fedora-28, Linux kernel version 4.15.0-00049, and gcc-7.3.…
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Hi,
I compile riscv-qemu as described in Wiki page
git clone --recursive https://github.com/riscv/riscv-qemu.git
cd riscv-qemu
./configure \
--target-list=riscv64-softmmu,riscv32-softmmu,ri…
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hi all,when i build RoCCExampleConfig emulator, i meet some exception, hope anyone can help me,thank you!
here is what i type:
> cd emulator
> make CONFIG=RoccExampleConfig
and the error is …
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I tool the latest Zynq-FPGA for Boom from https://github.com/donggyukim/fpga-zynq. Unfortunately, it does not support emulator for Boom core. Therefore, I imported "verisim" folder and its dependencie…
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Would someone be able to help me with running the rocket chip using custom C code?
I am working with another individual on creating an RoCC accelerator for calculating the CRC across a block of dat…
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Hi.
I have tried several times to run "make" under rocket-chip/emulator. I have cloned the latest version in 2018/3/2. I have clone the project and done each step just as what the README.md saied, …
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@kraj
[bitbake-cookerdaemon.log](https://github.com/riscv/meta-riscv/files/2407884/bitbake-cookerdaemon.log)
I open new issue about #33 .
start run build with command
$ bitbake core-image-…
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Hi,
I am looking for UART driver address location and related information. I do find options to configure UART at different location for luminarymicro. Is there something similar there for RISCV po…
ghost updated
6 years ago
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I've seen the .json file generated in emulator(using DefaultConfig):
`{"#address-cells":[1],"#size-cells":[1],"compatible":["freechips,rocketchip-unknown-dev"],"cpus":{"#address-cells":[1],"#size-cel…
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Dear all,
I post this here in riscv-qemu and in riscv-gnu-toolchain.
Can someone explain me simply how to make the user-space hello-world init working in qemu-system-riscv64 :
```
#include
…