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I'm trying to think about how to deal with generators whose parameters need to be calculated by a different generator. This is necessary to mix different verilog-generating languages, and also to be …
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The free SH2 core- aka J-core- is written in VHDL. In principle, J-core/SH2 should work already with Xilinx cores- someone just needs to port the Wishbone interface, startup code, etc :).
For ice40…
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If you use migen under Python 3.7+, you get this confusing error message:
```
D:\Code\fomu\foboot-bitstream\deps\migen\migen\fhdl\structure.py:484: DeprecationWarning: Using or importing the ABCs …
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I have installed pyFDA 2.0.2a using the mentioned methods. Program launches with pyfdax command, but Plot Tabs are not displayed. I have tried several times, both after cleaning the cashed repositori…
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When trying to build the HDMI2USB-litex-video video targets on the Nexys Video we get the following error;
```
CC boot-helper-lm32.o
LD firmware.elf
chmod -x firmware.elf
OBJCOPY…
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ISE is currently generating both working and non-working firmware from the same git commit to the repo.
Version v0.0.0-606-gebbfdc5 was built twice on Travis, the [first version](https://github.com/t…
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**Issue by [Fatsie](https://github.com/Fatsie)**
_Friday Jul 05, 2019 at 09:17 GMT_
_Originally opened as https://github.com/m-labs/nmigen-boards/pull/15_
----
This is current state for the [Digile…
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@xobs came up with the idea of using Etherbone over the USB SETUP packets using a vendor extension.
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Implement `build.platform` module.
- [x] `IOProxy`: proxy module, consumes *migen* `io` declaration.
- [x] `cli`: integrate as `-project`.
- [x] `Constraint.get_xdc`: returns *XDC* constraints.
…
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https://github.com/m-labs/migen/commit/bef9dea4cbf5a11b28bc7151e4d078c52944a41a