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https://github.com/lnis-uofu/OpenFPGA/blob/b16de387f92d132ccc0d9b682aab1c64e15e39ea/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga#L58
This part:
--bitst…
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To ease
- Tracking issues (categorize problems, reproduce bugs etc.)
- Manage pull requests (link issues, assign code reviewers, checklist)
We definitely need
- An issue template (which is tune…
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Hello!
Is there any way to get RTLIL or AST from VHDL sources?
I looked at this: https://www.reddit.com/r/yosys/comments/c46qjc/vhdl_ast_representation_and_rtil_conversion/
Does anyone know …
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https://github.com/lnis-uofu/OpenFPGA/blob/36113d35ac38e9ce10cec45dfbd18cac9e0c12de/openfpga_flow/scripts/run_fpga_task.py#L177
Traceback (most recent call last):
File "openfpga_flow/scripts/run…
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```
==> Upgrading twam/openfpga/prjoxide 20210325 -> 20210526
==> Downloading https://github.com/gatecat/prjoxide-db/archive/30c1f1de1af5d2c4fcb9d13a59e756d3f9d667
Already downloaded: /Users/nis/Li…
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I have purchased 5 of the QMTech boards for work purposes (arriving later this week), so should be able to use one to experiment with the open source flow. I also have (limited) access to the Genesy…
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**Describe the bug**
Hello,
I am running into the following error when trying to compile OpenFPGA for the first time (also attached in the screenshot):
In file included from /home/shay/a/iqbal11…
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**Is your feature request related to a problem? Please describe.**
Currently, OpenFPGA's Verilog testbench generator has a major problem
- The bitstream is hardcoded in the full testbenches which ca…
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When I finished make all command of OpenFPGA, it successfully finishes it seems. I have already installed all dependencies seems on the page. However it gives error during first verification.
the er…
ghost updated
3 years ago
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Which part of OpenFPGA is buggy:
--- >Documentation
Hi,
I'm trying to install OpenFPGA on my laptop (with Ubuntu 21.04) following all steps mentioned in the tutorial "OpenFPGA tutorial: How to …