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After building a rocket-chip emulator with the RoCC examples baked in,i can't run the test"**time emulator-freechips.rocketchip.system-RoccExampleConfig -c pk ./build/test-accumulator**" and **"emulat…
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Author Name: **Abdullah Raza Khan** (@arkhan91)
Original Redmine Message: 2493 from https://www.veripool.org
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I know we can create the c++ model of hardware in verilator. If I have genera…
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I tried to build a dual-rocket environment these days. I checked out the master branch of this repository, and the commit id is [8c6e745](https://github.com/freechipsproject/rocket-chip/tree/8c6e745).…
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Hi, I tried installing BOOM for my assignment and I have an error while running the make command (make run CONFIG=BOOMConfig).
Makefrag-verilator:68: recipe for target 'emulator-rocketchip-BOOMConfig…
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Hello,
I'm trying to build according instructions and I get following errors:
`g++ -O1 -std=c++11 -g -I/home/zhani/riscv-sodor/emulator/common -I/usr/local/include -Igenerated-src -c -o htif_e…
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I have just already built the C emulator without any problems.Then,I continued to following the rocket-chip READM.md.After typing "cd ./vsim" and "make ",I got an error like this：
/bin/bash: lin…
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Hi,
I use the following commands to build the emulator.
cd verisim
make CONFIG=PWMConfig
However, it cannot build successfully with errors.
error message:
make VM_PARALLEL_BUILDS=1 -C /us…
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Hi slavaim,
It's awesome to see that you have port zircon(magenta) to riscv!!!
I want to try it on the spike, could you give me any instructions to do it?
Thanks a lot!
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Hi, I clone the latest version from master branch at 2017.1.17.
Then I follow the README.md part to build emulator. However, it fails with some errors happen.
error message:
/project-template/testc…
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Yesterday, I run Linux on FPGA with BOOM-core successfully. While I want to learn how the tool-chain works out, I surprisingly find that I cannot generate .out files.
Here is the output:
`
[lipn@…