ucb-bar riscv-sodor issues

ucb-bar / riscv-sodor

educational microarchitectures for risc-v isa

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Data misalignment detection different for LBU vs LB instruction

#84 viniul opened 3 weeks ago
1
Implementing rv64 for the sodor core: Purpose of SodorScratchpadAdapter's restriction to 32-bit addresses?

#83 viniul closed 3 weeks ago
0
ERROR: Active region did not converge when run simulation

#82 tangjiaping opened 5 months ago
0
remove old slli/srai/srli opcodes

#81 buggy213 closed 8 months ago
0
Update for latest Rocket-chip APIs

#80 jerryz123 closed 8 months ago
0
Bump rocketchip

#79 jerryz123 closed 1 year ago
0
Better support for SBT assembly

#78 abejgonzalez closed 1 year ago
0
Bump to latest rocket-chip/chisel3.5.6

#77 jerryz123 closed 1 year ago
0
Fix SLLI/SRAI/SRLI microcode labels

#76 a0u closed 1 year ago
0
Rename insts called module

#75 joonho3020 closed 1 year ago
0
Bump to scala 2.13/chisel 3.5.5/latest rocketchip

#74 jerryz123 closed 1 year ago
0
fix: chisel3 pr #2758

#73 SingularityKChen closed 1 year ago
0
remove objectmodule

#72 sequencer closed 2 years ago
0
[DO NOT MERGE] Chisel 3.5 bump

#71 abejgonzalez closed 2 years ago
0
Fix hazard tracking when full_stall for 5stage

#70 jerryz123 closed 2 years ago
0
Merge all bump PR together

#69 sequencer closed 2 years ago
0
bump for chipsalliance/rocket-chip#2841

#68 sequencer closed 2 years ago
0
remove cloneType

#67 sequencer closed 2 years ago
0
Chisel 3.5 Bump

#66 abejgonzalez closed 2 years ago
0
I get the following error while executing a simulation of the Sodor 1-stage processor running the Towers of Hanoi benchmark

#65 advancedengineering opened 3 years ago
2
No emulator directory??

#64 Kian75 closed 3 years ago
2
fix for deprecation.

#63 sequencer closed 3 years ago
1
Fix off-by-one error with uaddr bitwidth calculation

#62 a0u closed 3 years ago
0
why is this named after the beloved island home of thomas the tank engine and friends?

#61 WhirligigGirl closed 3 years ago
1
Update SodorCoreParams for RC additions

#60 timsnyder-siv closed 3 years ago
1
Bump for RC Nov. / Chisel 3.4 / FIRRTL 1.4

#59 abejgonzalez closed 3 years ago
0
make run emulator error

#58 hz0ne opened 3 years ago
8
Out of time during test rv32ui-p-simple

#57 Phantom1003 closed 4 years ago
2
Chipyard Integration

#56 zitaofang closed 4 years ago
3
race condition in SimDTM.v under Verilator; related to "taddr-4" in fesvr/dtm.cc, write_chunk

#55 smcpeak opened 4 years ago
0
Update trace infrastructure

#54 a0u closed 4 years ago
0
Update riscv-tests

#53 a0u closed 4 years ago
0
Update fesvr

#52 a0u closed 4 years ago
0
Remove deprecated (and now erroring) usage of Module(reset).

#51 ucbjrl closed 5 years ago
0
bit patterns of shift immediate instructions

#50 miguelbarao opened 5 years ago
2
make run-tmulator fails

#49 farhadmerchant opened 5 years ago
2
error when compile riscv-sodor/riscv-tests/benchmarks with XLEN=32

#48 Lucas-Wye closed 4 years ago
0
Bump riscv-tests

#47 albert-magyar closed 4 years ago
1
Remove trailing whitespace from l Scala files.

#46 maloneymr closed 5 years ago
0
Build error verilator

#45 Mixermachine opened 5 years ago
2
Update sbt version.

#44 ucbjrl closed 5 years ago
0
No functional changes - update deprecated chisel3 usage

#43 ucbjrl closed 5 years ago
1
Support new C++ compilers.

#42 ucbjrl closed 5 years ago
1
Reports or tracing summary

#41 yanyh15 opened 6 years ago
0
Data memory mem_rw and mem_val

#40 AlefCS opened 6 years ago
0
Remove unneeded muxes

#39 edwardcwang closed 6 years ago
1
csignals lookup table has wrong op1 and op2 sel for JALR.

#38 ZiCog opened 6 years ago
1
fix bug: ‘string’ does not name a type;

#37 higuoxing closed 5 years ago
4
Why is it necessary to use RISCV_LINK_OPTS for compilation?

#36 ghost opened 6 years ago
0
add documentation and refactor debug.scala

#35 codelec closed 6 years ago
0