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Por medio de una lluvia de ideas vamos a determinar el listado de productos que se van a comprar cada mes
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I have a board using the LP1K-CB121 and would like to use apio to compile it. It is a custom board for a specific project, but I believe it only matters about the chip itself in order to add support?
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I've tried to extend the apio SConstruct to also support a VHDL toolchain, making use of yosys and the ghdl-yosys-plugin for synthesis. For simulation, plain ghdl is used instead.
The code is [here…
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### Feature Description
TL;DR, add to the yosys show command a flag to generate a simplified diagram.
Generating a graph with the ``show`` command to visualizing the design is a feature that helps…
zapta updated
7 months ago
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### ⚠️ Please verify that this feature request has NOT been suggested before.
- [X] I checked and didn't find similar feature request
### 🏷️ Feature Request Type
New Notification
### 🔖 Feature des…
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As I have seen in many contests, APIO 2009, COCI, ... ,
they show every single "SAMPLE" grading status, whether passed or failed.
But in this grader, the messages shows as a whole task.
So it wo…
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This is a proposal for discussion.
The idea is to switch the linter from Verilator to Veriable.
https://github.com/chipsalliance/verible
Rationale
In addition to a command line lint, Verible…
zapta updated
6 months ago
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The driver for the ulx3s board in Windows does no need to be installed with zadig (that is now automatically executed when the drivers are configured). If the libusbk (from zadig) is installed, the bi…
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Use apio 0.5.6, I get the error as seen in the image - if I use 0.4.1 however on the the BX at least all is good
![RS error](https://user-images.githubusercontent.com/60004943/101794339-c525d200-3ad4…