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I remembered one idea on how to do this based on our meeting with priyanka
Supposed we had this circuit
```verilog
module coreir_add #(parameter width=1) (
input [width-1:0] in0,
input [wid…
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The generation of individual verilog files can be handled at the coreir level, unless someone explicitly requires generating multiple coreir files.
There's also a request for generating file lists,…
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@jeffsetter now unsharp has an error in its compute units:
```bash
ERROR in compute unit: hcompute_ratio_stencil
in0_blur_unnormalized_stencil[0] -> 63743
in0_blur_unnormalized_stencil[0] -> 1…
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Tentative features for next major release of Magma
- [ ] New type system
- [x] bracket syntax Bits[n] instead of Bits(n)
- [x] product types
- [ ] sum types
- [x] Consistent with hw…
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They are two separate sets of tests for operators
1. tests/test_mantle40/test_common/test_operator.py
1. tests/test_coreir/test_operator.py
These should be consolidated and used by both implement…
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There is a bug in both the CoreIR simulator (accessed through magma) and the Verilator simulator (accessed through fault) with an and gate that is receiving mismatched signals.
There were two sign…
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I am using coreIR to generate a memory placeholder in RTL for further power analysis.
I want the RTL module which coreIR generator generated have the specific name matching with RTL implementation. …
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https://github.com/masc-ucsc/lgraph
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https://github.com/David-Durst/aetherling/blob/sim_issues/tests/helper_test_readyvalid.py#L54
It would be incredibly helpful if this worked. I think this requires changing both Magma and CoreIR.