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I have 8 years of experience in VLSI and EDA.
I don't have a lot of experience with FPGAs, I used my de1-soc for my final thesis at the university and haven't used it ever since.
I am very interes…
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I followed the installation steps for both DE1 images (i.e. 20190521_DE1_0.2.0b.img and 20200124_DE1_v0.2.1.img) and I cannot ssh into the FPGA. In fact, I cannot even log into the board via the seria…
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I implemented a small extension to allow the user to input their own custom application options to the External component.
Currently only for GHDL.
Check my fork in https://github.com/ibfelzmann/D…
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This source is supposed to be compiled on Intel FPGA SDK for OpenCL but I am getting following error for arria 10. I am using following version of the Intel(R) FPGA SDK for OpenCL(TM), 64-Bit Offline …
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Thanks for this great port. I managed to easily make it work on my DE1-SOC following your instructions.
I tested it on a VGA monitor and it worked out of the box, however I am trying to connect it to…
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Hello,
Thank you for creating this nice repo.. it's been very helpful. I tried to build my sd image with the following command and it failed. I followed every step in your tutorial exactly, and I am …
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While the mnist convolutional network demo runs for me I get an error on the others, for example the max pooling example. It seems that there is a file missing:
IOError: [Errno 2] No such file or d…
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Mr Thinkoco, some questions about HowToBuildBSP.md，希望在有空的时候可以指导下，3KS
1）在添加8bit LED_PIO之前，其实你还添加了avalon-mm pipeline bridge, So how about the Pipeline's configuration(Width, Address and so on)
2）在第9点…
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Hi there!
I am following the development of the MiSTer ports to DE10-Standard and DE1-SoC very closely. I am a FPGA developer myself and just got hold of a DE10-lite board with the MAX10 on it.
I …