danielholanda LeFlow issues

danielholanda / LeFlow

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

Other

588 stars 101 forks source link

issues

Newest

Newest Most commented Recently updated Oldest Least commented Least recently updated

not supported a supported wheel on this platform

#43 asm3344 opened 2 years ago
0
Unsupported Wheel Issue

#42 jayroopramesh opened 2 years ago
2
Access HDL code

#41 mahdieghane closed 2 years ago
1
Unsupported wheel on virtual machine

#40 hernandezurbina opened 3 years ago
3
fpga performance

#39 soans1994 closed 3 years ago
3
Missing module copysignf

#38 phatberstromgg opened 3 years ago
1
Deep Lab V3 and testings

#37 amitnh closed 3 years ago
1
Cannot run tests

#36 habibagamal closed 3 years ago
3
Legup 4.0 virtual image is not accessible

#35 LinasEin opened 4 years ago
6
Issues with generating Verilog for some complex examples

#34 SumantSakhalkar closed 4 years ago
0
Using Xilinx FPGAs and AXI memory interfaces

#33 ivanfv closed 4 years ago
2
Documents/short-guides for hardware bridging ?

#32 Ruinland closed 4 years ago
1
ERROR: Legup failed to generate Verilog

#31 phatberstromgg closed 4 years ago
5
I have everything installed but still i am getting this error while running "python test_all.py --fast"

#30 Sandeep2017 closed 4 years ago
8
Legup failed to generate Verilog

#29 mohitajais closed 4 years ago
1
How to use LeFlow for custom graph

#28 ChowderII closed 4 years ago
1
Xilinx support

#27 ChowderII closed 4 years ago
4
How to read memory_dump.txt

#26 alewarne closed 5 years ago
6
Cannot run some examples

#25 alewarne closed 5 years ago
8
What is the relationship between the return value of legup and the return value of tensorflow?

#24 cdyangzhenyu closed 5 years ago
6
How to make changes to the output

#23 dhritireddy closed 5 years ago
3
llvm: error: expected comma after...

#22 jk78346 closed 5 years ago
5
where shoud I give the input?

#21 hsiehchungting closed 5 years ago
3
FPGA integration

#20 BrayanBarrios closed 5 years ago
1
Are there any restrictions on the selection of FPGA version？

#19 janyChan closed 5 years ago
2
Unable to install tensorflow for LeFlow

#18 kratos6753 closed 5 years ago
2
LeFlow with new LegUP

#17 ghost closed 5 years ago
3
Raspi + Spartan 6

#16 dadrake3 closed 5 years ago
3
See the schematic

#15 roSimoes closed 5 years ago
6
Reduce ops fix

#14 santacml closed 5 years ago
1
Fail to generate IR for reduce_mean and reduce_max

#13 santacml closed 5 years ago
13
"No such file or directory 03_vecmul_b_f_files" during running test_all.py

#12 kp2377 closed 5 years ago
14
Windows & LegUp 6.x

#11 JohnnyOpcode closed 6 years ago
1
Devices

#10 jamesjjk closed 6 years ago
3
Trying feed AlexNet to LeFlow

#9 xzhou40 closed 5 years ago
4
Fixed MaxpoolingMNIST issue

#8 mahinlma closed 5 years ago
0
IOError: [Errno 2] No such file or directory

#7 mahinlma closed 6 years ago
3
Synthesis issue in classificationMNIST

#6 mahinlma closed 6 years ago
3
hardware generation issue with modelsim

#5 mahinlma closed 6 years ago
4
IOError: [Errno 2] No such file or directory - when try to run 01_vecmul_a.py test

#4 mahinlma closed 6 years ago
1
RUN TEST

#3 pocandraspoc closed 6 years ago
4
Issue while running test_all.py

#2 bagumondigi closed 6 years ago
5
Update README.md

#1 LucasBraganca closed 6 years ago
0