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Hosting Request
- Hosting Unit(Lab) Name: Digital Logic Design Lab
- Repository URL: https://github.com/virtual-labs/digital-logic-design-iiith
- Branch/Tag :[ master/v1.1.3](https://github.com/v…
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Defect Description :
In the "Electronics & Communications" discipline page of the open edx portal the lecture link given against the lab link is leading to wrong page. Where as the links should navi…
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Hello @R3dst0ne,
I have identified some errors in the snapcraft.yaml file that is used to create the Snap package for Logisim-evolution. The specific issues are as follows:
- The source URL for th…
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The current simulation of logic gates and Boolean algebra for DDCO (Digital Design and Circuit Optimization) in our MERN project is facing a critical performance issue. The algorithm used for calculat…
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Digital inputs are not an option since no I2S input is exposed, analog audio looks like the best option at this point. The STM32 on the Photon can trigger both its ADCs and DACs from the timer modules…
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Nice project, I was looking into doing something similar.
The schematics I found so far for interfacing with the Baofeng were quite different, the most important difference was about the PTT that was…
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### Team Name:
zer0dynamics
### Project Description:
Gradient ascent in function space (GRAFS) [1] is an algorithm for optimal control synthesis that leverages functional expansions of cont…
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## *Repository Creation Request*
Use this to get your experiment repository created or updated on GitHub under Virtual Labs organization.
1. #### Coordinating Institute:IIITH
2. #### Approver’s…
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### **Bug Reported on 3 November, 17:7 GMT +5:50 in**
Lab - Analog and Digital Electronics II
Experiment - To design a delay timer circuit using 555 timer IC
**Type(s) of Issue -**
* Incorrect Result…
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## *Repository Creation Request*
Use this to get your experiment repository created or updated on GitHub under Virtual Labs organization.
1. #### Coordinating Institute: IIT Roorkee
2. #### App…