-
### Describe the bug
I have a testcase design comprising a few I/O cells and 501 flop instances.
The SE pins of the flops are directly hooked-up to the internal output pin of an I/O cell.
Basicall…
-
https://github.com/google/xls/issues/861 has made enough progress that we should start documenting the RAM support properly.
https://github.com/google/xls/blob/main/xls/examples/delay.x can be used…
-
There is a spreadsheet @ [GF180MCU (GlobalFoundries 180nm PDK) -- Primitive Model Naming](https://docs.google.com/spreadsheets/d/1G88IhyqXGVu-BgH8hA-_N2YQnNiyPoPEqvXSOzmOaaY/edit#gid=1803291424) which…
-
we have just released a fully open source PDK for Globalfoundries 180nm process technology.
The repositories are now available under https://github.com/google - see https://github.com/google?q=glob…
-
-
## Expected Behavior
No Via resistance in tech lef
## Actual Behavior
Via resistance in tech lef
## Steps to Reproduce the Problem
1.
1.
1.
## Specifications
- Version:
- Platform:
-
If the intent was to follow the standard used by the sky130 PDK, then this is an epic fail. It needs correcting on multiple fronts.
For starters, the standard cell verilog modules make references …
-
There are a bunch of things which need to be applied to all the submodules of the gf180mcu-pdk. We should set up a robot which makes sure these files are kept in sync and deployed.
For the F4PGA pr…
-
It would be awesome to see how this CPU would work in ASIC form and Google is offering free tape outs to open source silicon projects on SkyWater's 130nm and GlobalFoundries 180nm MCU process technolo…
-
Deep mode DRC produces false positives on GF180MCU DRC CO.6a rule in latest KLayout. I'm attaching an archive with a minimized GDS from my Open MPW project where error manifests itself and a DRC scrip…