-
Probably dependent on https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/325
From http://www.clifford.at/icestorm/logic_tile.html
> Input lutff_i/in_3 can be configured to be dri…
-
In addition to a basic smoke test (#106), the CI should also exercise building, simulation, and synthesis.
To avoid the orpsoc-cores repo breaking these tests, a dummy test repo should be created. Ju…
-
After cloning, I run the icebreaker.py script in the soc folder with both --debug and --flash option, then with either and with none. I get the following error on Ubuntu 18.04
Warning: Wire top.ua…
-
Ok, this is one's on me...
I get odd behaviour if another thread (say, $100 io! ) is running a DO ... LOOP and I run another bit of code, also with a do loop...
(this requires a ice40-HX8K Breakout …
-
It compiled ok on one other PC I have, but I get the following error on my Laptop:
```
Compile nucleus...
tdp FF0 tcp 0
Compile Ice Cream Machine...
Free Pascal Compiler version 3.0.0 [2015/11/26] f…
-
### Version
emacs-plus@30
### Make sure to follow these steps before submitting the issue
- [X] run `brew update` and try to reproduce the issue again
- [X] run `brew doctor`, fix all issues and tr…
-
Here is a patch that will allow the boot loader to synthesize with Yosys. All of the changes are simple, and allow the RTL to pass Yosys rather strict syntax (parameter, assignment) and topology chec…
-
Hi there,
I've tried building from scratch as per the reference document here: https://github.com/jamesbowman/swapforth/raw/master/j1a/doc/j1a-reference.pdf
The Verilog seems to build and program O…
-
icetime can't parse new pcf options such as `-nowarn`, `-pullup`, and `-pullup-resistor`. It fails with the message:
```
// Reading input .pcf file..
icetime: icetime.cc:230: void read_pcf(const …
-
Currently we generate all the arch.xml files by either;
* Hand using XML includes
* @davesha1's Verilog to arch.xml generator.
As @jhol points out, it would be much easier to generate a lot of …