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The submodule "litex @ fbadfa1" uses an outdated URL in .gitmodules:
```
[submodule "litex/soc/software/compiler_rt"]
path = litex/soc/software/compiler_rt
url = https://git.llvm.org/git/compile…
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Could you please consider creating a release so that this software is suitable for distribution?
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This depends on https://github.com/hdl/bazel_rules_hdl/issues/1
- [x] Yosys (thus ABC?)
- [x] nextpnr
- [x] icestorm
- [x] Project Trellis
- [ ] Project Oxide
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As the arachne-pnr github says: Arachne-pnr is not maintained anymore; use nextpnr instead, which is a complete functional replacement with major improvements.
The commands to use nextpnr-ice40 wit…
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I'm hitting
nextpnr-ice40 -q --lp384 --package cm36 --pcf tinyfpga_bx.pcf --json servant_1.0.2.json --asc servant_1.0.2_next.asc
terminate called after throwing an instance of 'nextpnr_ic…
olofk updated
4 years ago
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icetime can't parse new pcf options such as `-nowarn`, `-pullup`, and `-pullup-resistor`. It fails with the message:
```
// Reading input .pcf file..
icetime: icetime.cc:230: void read_pcf(const …
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The guys who made the Mojo v3 FPGA (awesome FPGA for beginners at a low cost around the Spartan 6 XC6SLX9) are coming out with two new boards:
* https://alchitry.com/collections/all/products/alchit…
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From http://www.clifford.at/icestorm/logic_tile.html
> Clock, clock enable, and set/reset inputs are shared along the 8 logic cells. So is the bit that configures positive/negative edge for the fli…
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Hello, @zuloloxi , this j1a bitstream is amazing! It works on my Lattice IceStick. I loaded it with the icestorm tool. I've just been poking around, learning about Forth and admiring the fact that som…
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As of a94be4c, the ZeroSoC design barely fits on the iCE40UP5k FPGA I'm using for testing (on an [Icebreaker](https://www.crowdsupply.com/1bitsquared/icebreaker-fpga) dev board). We want to add additi…