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Hi,
I'm using fusesoc+edalize for synthesis on zynq mpsoc platform.
Now I would like to also simulate some of my subdesigns with xsim (or any other simulator for that matter), which is not a stra…
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Ｈi, do you mean that this project works fine on the fpga?
And I would appreciate it you could give some tutorial about how to build and install on an fpga?
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In the file /ref_files/src/main.cpp in line 48 it says:
`#define KRENEL_RESNET50 "resnet50_0"`
I assume it should say:
`#define KERNEL_RESNET50 "resnet50_0"`
And then later in line 227 sho…
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Dear IPBus developers,
I am working at the European Synchrotron (ESRF) in Grenoble, developing electronics for instrumentation and data acquisition systems. I had the opportunity to learn and use …
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i want using kvm in qemu-system-aarch64. when i set enable-kvm, a problem is raise:
qemu-system-aarch64: /qemu/exec.c:936: cpu_address_space_init: Assertion `asidx == 0 || !kvm_enabled()' failed
…
heixi updated
2 years ago
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If there is a plan to support u+ device?
Thanks so much!
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When updating a petalinux environment via `petalinux-config --get-hw-description .` I get an IndexError at your scripts in the post-process phase.
I added some smaller print statements inside the fil…
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We are using zynq Ultrascale + MPSoC with custom board.
Our board has 2 USB ports(Host 2.0 and device 3.0), 2 SDI(one input and another output).
Kernel version on board is 4.19.0 and In host PC 5.4.…
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I have 2 xilinx targets with MPSOC. multicore arm along side fpga. The 10G ethernet links the targets. This 10G ethernet is xilinx softcore on the fpga portion of SOC(system on chip). I have linux ru…
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I am trying to generate elf file from .pb(Tensorflow model) file for xilinx zcu104 board. If you have the proper steps and flow can you please share the same.
Thanks,