issues
search
ipbus
/
ipbus-firmware
Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol
https://ipbus.web.cern.ch
Other
41
stars
32
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
ZCU102 example design license issue with temac_gbe IP
#243
joschambach
closed
4 weeks ago
3
IPbus slave icap_us_usp gives data_valid always zero
#242
mkrivda
closed
5 months ago
2
A collection of small improvements
#241
jhegeman
closed
6 months ago
1
Use of VHDL-2019 Interfaces
#240
DavidMonk00
opened
7 months ago
0
Support SYSMONs for all SLRs for UltraScale and UltraScale+
#239
jhegeman
closed
6 months ago
4
Design not properly held in reset
#238
LukasGibeh
opened
8 months ago
5
Fix a missing port in a component declaration
#237
jhegeman
closed
8 months ago
2
Improve ipbus drp bridge
#236
jhegeman
closed
9 months ago
3
Fix ipbus clk bridge
#235
jhegeman
closed
10 months ago
2
Improve the (SGMII version of the) VCU118 infrastructure code
#234
jhegeman
closed
10 months ago
1
Add Xilinx/Vivado attributes to robustify the reset CDC
#233
jhegeman
closed
10 months ago
1
Add a minimal .gitignore file to ignore some swap and temporary files
#232
jhegeman
closed
10 months ago
0
IPBus read-out
#231
aranzaba
opened
10 months ago
3
Set source IP in DHCPDISCOVER packets
#230
LukasGibeh
opened
10 months ago
0
Source IP in DHCPDISCOVER packets
#229
LukasGibeh
opened
10 months ago
1
IPBus options with Zynq
#228
aranzaba
opened
11 months ago
2
RARP sometimes doesn`t work after power up or reboot of FPGA
#227
mkrivda
closed
5 months ago
25
Fix a few inconsistencies in the inline documentation
#226
jhegeman
closed
12 months ago
2
Improve the device DNA reading state machine
#225
jhegeman
closed
11 months ago
2
Remove spurious includes of the led_stretcher
#224
jhegeman
closed
1 year ago
1
Fix the oscillator clock frequency in the VCU118 SGMII infrastructure
#223
jhegeman
closed
1 year ago
2
"ipbb ipbus gendecoders" does not work
#221
abunickabhi
closed
1 year ago
7
Support for "Make the IPBus address decoder generator script accept empty nodes"
#220
jhegeman
closed
1 year ago
1
Frequency counter with separate reference clock
#219
tswilliams
closed
1 year ago
1
Enhancement/213
#218
dmnewbold
opened
1 year ago
0
Feature improve freq ctr
#217
jhegeman
closed
1 year ago
2
Add a lower-speed, CPLL-based version of the XDMA interface
#216
jhegeman
closed
1 year ago
1
Adding doc for syncreg
#215
dmnewbold
closed
2 years ago
0
Addition of notes on ipbus_syncreg_v
#214
dmnewbold
closed
2 years ago
0
Addition of axi4lite-ipbus and ipbus-axi4lite bridge designs
#213
dmnewbold
opened
2 years ago
0
Add support for DHCP with static reservation in DHCP server
#212
dpcsankey
closed
1 year ago
3
VCU118 SGMII example design: Fix termination settings of clock pins
#211
tswilliams
closed
2 years ago
1
Update IP checksum calculation to be compliant with RFC 1624
#210
dpcsankey
closed
1 year ago
2
IPBus on a Zynq FPGA
#209
andrea-celentano
opened
2 years ago
1
Suggestion: rename ipbus_cdc_reg(.vhd) to cdc_reg(.vhd)
#208
jhegeman
opened
2 years ago
0
DHCP support
#207
mwensing
closed
2 years ago
3
Fix XDMA bypass example project
#206
jhegeman
closed
2 years ago
1
The k800_xdmaBypass example project is broken
#205
jhegeman
closed
2 years ago
1
Use generics to specify PCI identifiers (instead of hard-coding them)
#204
jhegeman
closed
2 years ago
6
Add filter to sda input
#203
mffuchs
closed
3 years ago
0
Syncreg consolidation
#202
alessandrothea
closed
2 years ago
2
Switching CI jobs from vivado 2018.3 to 2020.2
#201
alessandrothea
closed
3 years ago
1
VC118 - Adding missing `rarp_select` signal
#200
alessandrothea
closed
3 years ago
1
107 example designs clock constraints - continued
#199
alessandrothea
closed
3 years ago
1
ipbus transport axi sim
#198
alessandrothea
closed
3 years ago
5
Exposing rarp select ports through infra interfaces
#197
alessandrothea
closed
3 years ago
2
ZCU 102 example LEDs debug leds
#196
alessandrothea
opened
3 years ago
0
Clock constraints for example design
#195
alessandrothea
closed
3 years ago
1
CI tests update
#194
alessandrothea
closed
3 years ago
3
axi bus implementation on top address space of ipbus
#193
ashoward
closed
3 years ago
1
Next