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Hi,
I'm a Computer Science Engineering student in Spain and I'm using RIPES for my final degree's project. My aim is to add a new processor model, which is described in System Verilog.
I am follow…
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In `./icebox/icebox_vlog.py`:
https://github.com/cliffordwolf/icestorm/blob/88eebff7db9d76e418ccbddd884c4e617596a428/icebox/icebox_vlog.py#L378
This doesn't respect `$(PREFIX)` during installati…
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Hi there,
Currently I am trying to synthesize PICORV32 onto DE0 Nano FPGA using Quartus Prime Lite.
I have no problem synthesizing with [synth_area_top.v](https://github.com/YosysHQ/picorv32/blo…
YapWC updated
4 months ago
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The ISA manual states that JALR should clear the LSB of the address:
> The indirect jump instruction JALR (jump and link register) uses the I-type encoding. The target
address is obtained by addin…
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@cliffordwolf @FSMaxB @gordon-quad
We need more examples, what do you all think we need to add? (hoping we could brainstorm, I also have some time this weekend to create stuff)
Some ideas:
- C->Ver…
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I was working on https://github.com/drtrigon/fpgarduino-icestorm and have setup a picorv32 with peripherials in order to emulate/mimic an arduino uno board. During this I came to the point where I wou…
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(I never dealt with Verilog before, I'm a software dev)
At https://github.com/cliffordwolf/picorv32/tree/master/picosoc (`README.md`) I see
> `make hx8ksim`
> `make hx8kprog`
I get:
> `yosys-co…
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Hello there,
when executing following command in the litex-boards directory, the NEORV32 CPU Type is compiled and flashed to my Arty A7-100T:
`./digilent_arty.py --variant=a7-100 --cpu-type=neorv3…
vogma updated
8 months ago
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There is support for `$test$plusargs : String -> ActionValue Bool` in Bluesim, which just returns whether an argument was provided on the command line with `+`, i.e. `sim.exe +foo` means `$test$plusar…
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This was working previously. Yesterday I updated litex, and since then I no longer get a .we read strobe when a CSRStatus is read.
I am using the picorv32 soft cpu. If I change to the vexriscv soft c…