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SystemVerilog's sequence construct seems very useful. It might not be useful to entirely copy the syntax but I'd like to capture it's powerful semantics. Perhaps it would be sufficient to take in a pr…
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Hi. Today most designs use some aspects of SystemVerilog, so how about setting the default to SV2012? An alternative thought would be to add a file that contains default switches.
Thanks, Randy
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We have some places in our code where we hackishly/partially parse (parts of) SystemVerilog. It would be nice to choose an existing parser and integrate it properly into the codebase.
Currently we …
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#5616 introduces a new, high(er) level way of defining format string and printing in CIRCT.
Currently, this has a somewhat simple lowering that _requires_ matching `PrintOp(FormatVerilogStringOp(...)…
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Hi! Congratulations on the tapeout.
In looking through your build system, it seems like you have checked in a synthesized netlist version of the core:
https://github.com/Hagiwara-shc/j202_soc/bl…
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I've installed `yosys`. I've installed the `systemverilog` plugin from `https://github.com/chipsalliance/synlig`.
I can load the plugin, but then it can't find the `top` module.
```
yosys -p "p…
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Veridian is currently the only SystemVerilog Language Server with autocompletion that works with Vim [as of November 2023], but no releases are available for windows devices. It would be great to have…
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Boa tarde,
legal esse Tamburetei!
Vou ficar olhando regularmente para incorporar aquilo que me parece útil na página de LOAC mesmo.
Quanto ao curso de Verilog da UTFPR, ele tem algumas informaçõe…
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Hi!
Is there a way to integrate autocompletion based on the tags file, such that if I typed `instance.` VSCode could autocomplete methods and variables from the instance's class?
Thank you for this …
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Please add syntax support for:
- VHDL
- Verilog
- SystemVerilog