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I am trying to implement rocket chip on zedboard. I have given rocket chip and testchipip's paths in ..common/Makefrag. Also, I have initialized the submodules. When I run the command 'make project' i…
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# Description
I'm trying to run behavioral simulation for ZHW on fccm-ae branch using target test_z3_behav.
```
make test_z3_behav
ERROR: [Vivado 12-172] File or Directory '/home3/shared/liu91/sys…
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https://forums.xilinx.com/t5/Embedded-Linux/Petalinux-2020-2-FPGA-manager-bootgen-failed/m-p/1239675/highlight/true#M50390
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Hi,
Can I run use this project with Zynq 7z020 FpGA with PL alone ? I read Artix-7 is the same fabric used in Zynq 7k FPGA and I have one readily available
Thanks
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https://hhuysqt.github.io/zynq1/
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Hello,
I am a master's student working on my Master's Thesis, and I am experiencing several issues while trying to compile the XRT library on a Debian 10 environment on a Zynq Ultraescale + XU8 Mer…
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For Shep/Herd, the ability to access the per-channel information of the FF is important to be able to debug any faulty links during a link/slice test.
Currently we have the IsPresent bits that let…
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ld/../benchmarks/mt-vvadd -I/root/fpga-zynq/rocket-chip/riscv-tools/riscv-tests/ …
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It is my understanding that Antmicro want to support the ZCU10[45] dev boards.
* [ZCU104](https://www.xilinx.com/products/boards-and-kits/zcu104.html) - Zynq UltraScale+ XCZU7EV-2FFVC1156 MPSoC
…
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hello ,I'm a new for zynq, why use the txs02612?
the zynq have two sd periph.