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### Steps to reproduce
1. Create a Python file with the following code:
```python
import collections
isinstance([], collections.Iterable)
```
2. Run pylint on that file
### Current behavi…
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Moving from https://github.com/m-labs/artiq/issues/1080#issuecomment-409607643
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Hello everyone. Have you ever dealt with this error? Any ideas how to fix it?
ImportError: /opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64/libstdc++.so.6: version `CXXABI_1.3.8' not found (required by /usr/l…
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You should mention in the README the dependency on migen and how to install it.
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It seems like there are currently mutiple efforts to interface Migen and LiteX with AXI + Zynq boards.
It would make this project a lot more findable if it was called something like `migen-zynq` or…
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As part of developing for Sayma_AMC [WUT is running ARTIQ](https://github.com/m-labs/sinara/issues/468), tweaking Migen/ARTIQ source and using the ARTIQ build toolchain. Likewise, M-Labs ought to be a…
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Before we send of the boards to manufacture, we should have a protoype of the CPLD logic ready and compiling so that we know it can in principle implement all the required functionality. We also need …
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```
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| \/ (_) ___| ___ / ___|
| |\/| | \___ \ / _ \| |
| | | | |___) | (_) | |___
|_| |_|_|____/ \___/ \____|
MiSoC Bootloader
Copyright (c) 2017-2018 M…
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gory details: https://irclog.whitequark.org/m-labs/2018-06-28
Summary:
- The sysref alignment scans aren't working properly.
- It seems as if the HMC7043 phases aren't adjusting correctly, even t…
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```python
from artiq.experiment import *
class SAWGTest(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("sawg1")
@kernel
def run…