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peteut
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migen-axi
AXI support for Migen/MiSoC
MIT License
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allow user-defined system clock
#30
sbourdeauducq
closed
1 year ago
2
Unbreak build and CI
#29
peteut
closed
1 year ago
0
ps7: remove unused por clock domain
#28
sbourdeauducq
closed
1 year ago
1
Axi2csr srams
#27
Spaqin
closed
2 years ago
2
AXI SRAM support
#26
Spaqin
closed
2 years ago
1
Bump py from 1.8.1 to 1.10.0
#25
dependabot[bot]
closed
2 years ago
0
Bump jinja2 from 2.10.3 to 2.11.3
#24
dependabot[bot]
closed
2 years ago
0
kasli_soc: add ddr signals
#23
astro
closed
3 years ago
1
platforms: add kasli_soc
#22
astro
closed
3 years ago
1
coraz7: rename to accommodate both device variants
#21
astro
closed
3 years ago
1
add Red Pitaya platform
#20
sbourdeauducq
closed
3 years ago
3
soc_core: add config logic from misoc
#19
sbourdeauducq
closed
3 years ago
0
fix compatibility with recent MiSoC
#18
sbourdeauducq
closed
4 years ago
0
platforms: add zc706 + coraz7_07s
#17
astro
closed
4 years ago
1
I would like use it with PYNQ board
#16
kdpatino
opened
4 years ago
1
compatibility with new MiSoC identifier core
#15
sbourdeauducq
closed
4 years ago
0
typo in soc_core.py
#14
sbourdeauducq
closed
4 years ago
0
Migen platform compatibility
#13
sbourdeauducq
closed
4 years ago
1
Channels Should be Stream Interfaces
#12
peteut
opened
5 years ago
0
High-Speed DMA Controller Peripheral
#11
peteut
opened
6 years ago
0
Add Documentation
#10
peteut
opened
6 years ago
0
Expose `dma[:].rst_n` from `PS7`
#9
peteut
closed
6 years ago
0
Is anyone working on this project a Uni student?
#8
mithro
opened
6 years ago
2
Consider rename from migen-formal to migen-axi or migen-zynq
#7
mithro
closed
6 years ago
3
misoc.interconnect.stream -> DMAC | PRI
#6
peteut
closed
6 years ago
4
CSR Shall Be Word Aligned
#5
peteut
closed
6 years ago
0
AXI2CSR W/ 16 Bits Bus
#4
peteut
closed
6 years ago
1
DT Overlay Generator
#3
peteut
opened
6 years ago
3
Tests for AXI2CSR
#2
peteut
closed
6 years ago
0
Add AXI4-Lite Bridge Module
#1
peteut
opened
6 years ago
2