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Hi Ben,
I would like to know, in your estimation, what would be the theoretical maximum prover throughput if I tiled a large FPGA (like an Alveo 280) with the BLS12-381 coprocessors. LUT utilisatio…
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I use Vitis AI to quantize my tensorflow model (CNN+FC). However, it only has 0.1 MB reduce from 39.6MB to 39.5MB.
I have also checked with other people who use it, and they have the same result.
…
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TCL in Vivado gives:
`Error reading json file ...../boards/Xilinx/au50/es/1.0/xitem.json`
The board is not present in this repo anymore
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I am on Ubuntu 18 with Vitis 19.2 .
I have an OpenCL kernel that I have built and run successfully on the Alveo U250.
Now, I have built XRT with the `-opt` deb package and installed it. Is there a…
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the src code and conn_250.ini file uses more DRAM banks than U250 actually supported (4).
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I am running syn_yosys.sh to reproduce the outlined flow. But looks like no timing reports were generated yet. However, I didn't see any obvious problems being reported up until the script looked for …
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Just poking around OpenCL/SYCL support in TF. Im wondering if I can use this fork of sycl as a backend to TF (and use 2019.2 v++ in the intermediate stage) and target the Alveo U2xx devices ? Thx
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Hi,
I was trying to run the PLRAM example in the repo, and ran into some issues when compiling it with v++. When I compile the source directly, as https://github.com/Xilinx/Vitis_Accel_Examples/blo…
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Hello,
I am trying to compile the hello_world example in Nimbix following instructions https://alveo.readthedocs.io/en/latest/vitis/.
To my surprise the compilation with
TMP_WORK_DIR=$(mktem…
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Hi,
I noticed that in the submodule/cmac directory, it created two CMAC IPs, for example,
```
alveou200_board = cmac_ALVEOu200_0 cmac_ALVEOu200_1
```
However, it seems only one has been in…