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Before we send of the boards to manufacture, we should have a protoype of the CPLD logic ready and compiling so that we know it can in principle implement all the required functionality. We also need …
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```
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| \/ (_) ___| ___ / ___|
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| | | | |___) | (_) | |___
|_| |_|_|____/ \___/ \____|
MiSoC Bootloader
Copyright (c) 2017-2018 M…
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gory details: https://irclog.whitequark.org/m-labs/2018-06-28
Summary:
- The sysref alignment scans aren't working properly.
- It seems as if the HMC7043 phases aren't adjusting correctly, even t…
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```python
from artiq.experiment import *
class SAWGTest(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("sawg1")
@kernel
def run…
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```
$ ./artiq/gateware/targets/sayma_amc.py
Traceback (most recent call last):
File "./artiq/gateware/targets/sayma_amc.py", line 485, in
main()
File "./artiq/gateware/targets/sayma_amc…
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* DAC signal is present at the SMP connectors
* No signal visible at the Allaki SMA connectors
* The problem is on the Sayma side (as can be demonstrated by swapping Allakis)
* Could be a problem w…
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S7DDRPHY works with:
- DDR2 / 2 phases / BL4.
- DDR3 / 4 phases / BL8.
To support DDR3 / 2 phases / BL8, the PHY needs some modifications.
Here is an old modified version of the PHY that has t…
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Running ARTIQ built from 8fd57e6ccb6e5070d3dc988a9d5550b295621d72. Board boots, Ethernet ping works (0% packet loss) and HMC830 lock is fine. Running the following ARTIQ python program. Looking at SMP…
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When running artiq_flash:
```
Info : sector 232 took 618 ms
Info : sector 233 took 623 ms
Info : sector 234 took 618 ms
Info : sector 235 took 624 ms
Info : sector 236 took 624 ms
Info : sector…
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Context:
- There are a situations where it's useful to have EEMs physically separated from the Kasli that controls them by some meters.
- e.g. for the laser servo, we will probably have Kasli in th…