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In my core, I use Symbiflow tool to synthesize and generate bitstream to an Artix 7 FPGA.
I recently needed to pass a vlogdefine to Yosys due to memory initialization but the parameter is not passe…
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When first run `make prog`, it will take a long time (about 6~7 mins) to finish synthesis, place&route, etc. I find out that during this process, only one CPU core is used, leaving other 7 cores idle.…
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References the XDC [tutorial](https://github.com/byuccl/digital_design_colab/blob/329c110769676161aa1e57ad0d35753fa46d6f34/Tutorials/xdc_tutorial/xdc_tutorial.ipynb#L2)
Formatting issue - Not gener…
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## Expected Behavior
I want the menu to retain the state of whicever submenus I've expanded. This would make browsing the documentation less frustrating.
## Actual Behavior
I start with a fully…
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When the code was compiled using Surelog-yosys plugin, the bitstream was generated, but would not work properly. The State Machine would not cycle through, which caused each button on the counter to o…
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This example SoC build well with f4pga and Vivado, but does not terminate with default settings:
[https://github.com/chili-chips-ba/openXC7-TetriSaraj.git
29a8501669b167c55efc5da87a8ae7402271d986](h…
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The CI workflow in this repo takes ~10h to run. On the one hand, that's because running some of the tasks on the largest architectures (xc7200t) takes 5h. On the other hand, job `install` is executed …
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I got an error like the title. The detailed error information is like this
`ERROR: /root/yosys-uhdm-plugin-integration/UHDM-integration-tests/tests/orv64/rtl/common/pygmy_func.sv:24: Encountered unh…
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The downloads page that the doc points to no longer exists.
https://cfu-playground.readthedocs.io/en/latest/vivado-install.html
points to
https://www.xilinx.com/support/download/index.html/c…
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Hi there, not sure how easy is to add another board to this program, normaly you have to use [Vivado](https://www.xilinx.com/products/design-tools/vivado.html)
but I wanted to try Icestudio it seem…