-
I just cloned chisel-testers and tried to run `sbt` and got the following errors:
````
[warn] ::::::::::::::::::::::::::::::::::::::::::::::
[warn] :: UNRESOLVED DEPENDENCIES :…
-
**Type of issue**: Feature Request
**Is your feature request related to a problem? Please describe.**
Following https://github.com/chipsalliance/chisel/issues/1718, verification IRs are guar…
-
Cover statements are not yet possible. Something like:
```scala
class Foo() extends Module {
val out = IO(Output(Bool()))
val i = Counter(10)
out := i === 9
cover(out)
}
```
verif…
-
The CombDataflow op interface is being used only in the FIRRTL dialect, `CheckCombLoops` pass, resolve the downstream dependencies to ensure the interface can be defined in the FIRRTL dialect.
Relate…
-
I've noticed that a few FIRRTL transforms take a good amount of time to run (depending on the design, of course). One of the most expensive ones is consistently `DedupModules`, which [runs before High…
-
While the other better way is to merge the wake files into chisel3 and firrtl
-
The following is currently failing:
```
FIRRTL version 4.0.0
circuit Foo:
module Foo:
wire x: UInt
node y = {|some: UInt, None|}(Some, x)
```
~The problem is that this is parsing…
-
Implement all Primitive Operations in Firrtl [spec](https://github.com/freechipsproject/firrtl/blob/master/spec/spec.pdf)
Then we can parse firrtl, dynamically build the circuit by components, then w…
-
Currently I'm trying to understand the way to add a DMA device into chipyard design. Based on the suggestion in https://github.com/ucb-bar/chipyard/issues/9, I have started with the example of BlockDe…
-
Forgive me, I'm new to Chisel, so this could be user error.
I am struggling to get testing to work. I get tons of warnings that look like this:
```
WARNING: external module "AsyncResetReg"(tl.c…