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Currently I'm trying to understand the way to add a DMA device into chipyard design. Based on the suggestion in https://github.com/ucb-bar/chipyard/issues/9, I have started with the example of BlockDe…
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Branches
| project | branch |
| ------- | ------- |
| firrtl | intervals |
| chisel3 | interval-type-2 |
| firrtl-interpreter | instrumenting-sizes |
chick updated
7 years ago
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Currently SystemVerilog modules are the only artifacts being produced with Utopia HLS. Additional output formats should be considered:
* ~Unscheduled DFCIR~ Closed with #25 and #31.
* ~Scheduled F…
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**Type of issue**: Feature Request
**Is your feature request related to a problem? Please describe.**
Following https://github.com/chipsalliance/chisel/issues/1718, verification IRs are guar…
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Consider this MLIR example:
```
module {
firrtl.circuit "OMIRField" {
firrtl.module @OMIRField(in %x_b: !firrtl.uint, out %y_b: !firrtl.uint) {
%n_b = firrtl.node sym @omir_sym %x_b…
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This project aims to apply information found using the firrtl interpreter's run-time instrumentation of values passing through a node.
- Run a firrtl circuit with instrumentation turned on
- This …
chick updated
7 years ago
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The FIRRTL grammar is context sensitive. While not insanely critical, it could help catch parsing bugs if there's an option to generate identifiers that use known FIRRTL keywords.
E.g., the followi…
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Implement all Primitive Operations in Firrtl [spec](https://github.com/freechipsproject/firrtl/blob/master/spec/spec.pdf)
Then we can parse firrtl, dynamically build the circuit by components, then w…
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Given:
```fir
FIRRTL version 3.0.0
circuit Foo: %[[
{"class":"sifive.enterprise.firrtl.FullAsyncResetAnnotation", "target":"~Foo|Foo>reset"}
]]
module Foo:
input p : UInt
input r :…
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Since Chisel has supported LTL via intmodule, I think it might be a good idea to upstream LTL as a part of firrtl spec. This cleans up the fir file generation, and makes LTL->SVA flow more clean and e…