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While the current SPI.h tries to safe-limit the maximum SPI clock frequency of the SAMD core, it does so in a weird way, assuming F_CPU to be always 48000000L and only for the SAMD21G18A part.
https:/…
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I have an Alchitry Au board. Board design is set to 100Mhz clock, which matches the HW clock on the board. The greatest synthesis frequency I can pick is 2 Mhz. Why is that?
Next, at 2Mhz, when I s…
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Hi, I am working on the hello world test of "lowrisc-chip". The branch that I am working on is kc705_update. The problem is that I can generate the bitstream file and combine it with the "hello world"…
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Hi Jim,
what do you think about adding these features to the CreateClock function?
1.) Add an enable port to be able to start and stop the clock signal
2.) Add the possibility to choose with which …
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I was just testing out RPiTX with the different modes, i think the SSTV test might have the same issue.
it transmits ok on like 3.845 or 3.835 and ect., but if i try anything like 384 or 3.842, it'…
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## Type of issue
Enhancement
## Description
Wakeup sources like CEC and CIR need an accurate clock to do protocol decoding. Boards without external OSC32K get OSC32K divided from OSC16M. Sinc…
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Configuration: ESP32 Dev Kit
The comments in the README and in the source code say that the iBus should be polled at least once per 1 ms.
When a timer is used the library uses the following code:
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Audio examples for most elements of each sound channel would greatly help to understand what it actually does and put it in some hearable perspective, but also present how some parameters will act or …
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In the Teensy 4 sources, the code that initializes the FLEXIO2 peripheral configures an invalid clock setting according to the IMXRT1062 reference manual. I'm curious if this setting is intentional an…
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default bitrate inside spi lib is 4MHz and is stable between sending bits
but when setClockDivider are used, CLK signal is unstable and giving strange frequency.
img -> default spi lib with bitrate = …