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I would like to use the uart bridge (for openocd debugging and for litescope).
So I changed my target file (atlys/base) and added:
```
[...]
def __init__(self, platform, **kwargs):
kwargs['u…
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OS: `Ubuntu 22.04.3 LTS`
Toolchain: `riscv64-unknown-elf-gcc (g2ee5e430018) 12.2.0`, `riscv64-unknown-linux-gnu-gcc (g2ee5e430018) 12.2.0`, etc.
-> built from [source](https://github.com/riscv-colla…
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Trying to install a fresh copy of litex is failing:
./litex_setup.py --init --install --user --config=full
........
[ 111.121] Installing liteiclink Git repository...
Obtaining file:///home/pr…
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LiteX has added more CPU cores since this was last updated -- see https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/cpu
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Hi,
in the Readme in the RiscV toolchain section https://github.com/litex-hub/linux-on-litex-vexriscv/blob/3d99c8ec1ba5b5525e4826196e5878cc15e68802/README.md?plain=1#L122 an old Toolchain release wit…
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This issue concerns the [Migen/LiteX](https://github.com/im-tomu/fomu-workshop/blob/master/docs/migen.rst) page of thu tutorial.
It was not clear where I had to copy paste the extra Python code for…
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I have followed the instructions in the readme so far but when it comes to loading the bitstream to the Arty A7-100 I get errors.
When I run `./make.py --board=arty --load` i get this error:
`Tr…
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Hello,
I am experiencing an issue when running the console with the CVA5 CPU using the script .`/litex_sim.py --cpu-type cva5 --with-sdram`. The console consistently freezes after typing just a few…
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# Brief explanation
Migen / LiteX doesn't quite follow pep8 / pylint for good reasons. Extend pep8 and/or pylint to understand when it should allow violations. Extra additional checks for good Mige…
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Hi the download environment script never goes as far as installing the litex suite because it fails to clone liteusb. Is liteusb no longer a thing? I'm getting a 404 from https://github.com/enjoy-digi…